AD14060

Obsolete

480-MFLOP, Quad DSP, 5 V, CQFP Package

Data Sheet (Rev. B) Product Selection Table

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Part Details

ADSP-21060 core processor(x4)
480 MFLOPS peak, 320 MFLOPS sustained
25 ns instruction rate, single-cycle instruction execution-each of four processors
16 Mbit shared SRAM (internal to SHARCs)
4 gigawords addressable off-module memory

Twelve 40 Mbyte/s link ports (3 per SHARC)
Four 40 Mbit/s independent serial ports (one from each SHARC)
One 40 Mbit/s common serial port
5 V and 3.3 V operation
32-bit single precision and 40-bit extended precision IEEE floating point Data formats, or 32-bit fixed point data format
IEEE JTAG Standard 1149.1 test access port and on-chip emulation

Documentation

Data Sheet 2

AD14060/AD14060L: Quad-SHARC ™ DSP Multiprocessor Family Data Sheet (Rev.B) 12/01/2004

AD14060 5V Military Data Sheet 11/13/2002

Technical Articles 2

Multi-Channel Analog-to-Digital Converter Module Integration 10/01/2001

Class T Satellite Products 10/01/2001

Cross Reference Guide 4

Military Products by Function 01/22/2009

Military Products by GENERIC Part Number 01/22/2009

SMD to Generic Cross Reference 01/22/2009

Military Part Cross-Reference Guide 01/22/2009

Software Manual 1

VisualDSP++^® 5.0 C/C++ Compiler Manual for SHARC^® Processors (Rev.1.5) 11/13/2009
- Documentation Errata

This is the most up-to-date revision of the Data Sheet.

Software Resources

Software & Tools Anomaly 1

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