AD9545
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AD9545

Quad Input, 10-Output, Dual DPLL/IEEE 1588, 1 pps Synchronizer and Jitter Cleaner

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 2
1ku List Price Starting From $19.21
Features
  • Dual DPLL synchronizes 1 Hz to 750 MHz physical layer clocks, providing frequency translation with jitter cleaning of noisy references
  • Complies with ITU-T G.8262 and Telcordia GR-253
  • Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2
  • Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb (5 × 10−8)
  • Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus
  • Programmable digital loop filter bandwidth: 10−4Hz to 1850Hz
  • 2 independent, programmable auxiliary NCOs (1 Hz to 65,535 Hz, resolution < 1.37 × 10−12 Hz), suitable for IEEE 1588 Version 2 servo feedback in PTP applications
  • Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation
  • Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported
  • 5 pairs of clock output pins with each pair usable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)
  • 2 differential or 4 single-ended input references
  • Crosspoint mux interconnects reference inputs to PLLs
  • Supports embedded (modulated) input/output clock signals
  • Fast DPLL locking modes
  • Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO
  • External EEPROM support for autonomous initialization
  • Single 1.8 V power supply operation with internal regulation
  • Built in temperature monitor and alarm and temperature compensation for enhanced zero delay performance
Additional Details
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The AD9545 supports existing and emerging International Telecommunications Union (ITU) standards for the delivery of frequency, phase, and time of day over service provider packet networks, including ITU-G.8262, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2.

The 10 clock outputs of the AD9545 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.

The AD9545 is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the −40°C to +85°C temperature range.

Note that throughout the data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.

APPLICATIONS

  • Global positioning system (GPS), PTP (IEEE 1588), and synchronous Ethernet (SyncE) jitter cleanup and synchronization
  • Optical transport networks (OTN), synchronous digital hierarchy (SDH), and macro and small cell base stations
  • Small base station clocking, including baseband and radio
  • Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
  • JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
  • Cable infrastructures
  • Carrier Ethernet
Part Models 2
1ku List Price Starting From $19.21

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Documentation

Documentation

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Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9545BCPZ
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AD9545BCPZ-REEL7
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Part Models

Product Lifecycle

PCN

Aug 8, 2022

- 22_0065

Data Sheet Revision for AD9543/AD9545/AD9546

Sep 21, 2020

- 20_0271

AD9545 specifications change as relates to the system clock input and usage of the 2x frequency multiplier.

AD9545BCPZ

PRODUCTION

AD9545BCPZ-REEL7

PRODUCTION

Sep 6, 2018

- 18_0109

AD9545 Data Sheet Specification Changes

AD9545BCPZ

PRODUCTION

AD9545BCPZ-REEL7

PRODUCTION

Filter by Model

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Reset Filters

Part Models

Product Lifecycle

PCN

Aug 8, 2022

- 22_0065

arrow down

Data Sheet Revision for AD9543/AD9545/AD9546

Sep 21, 2020

- 20_0271

arrow down

AD9545 specifications change as relates to the system clock input and usage of the 2x frequency multiplier.

AD9545BCPZ

PRODUCTION

AD9545BCPZ-REEL7

PRODUCTION

Sep 6, 2018

- 18_0109

arrow down

AD9545 Data Sheet Specification Changes

AD9545BCPZ

PRODUCTION

AD9545BCPZ-REEL7

PRODUCTION

Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 2

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EVAL-AD9545

AD9545 Evaluation Board

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EVAL-AD9545

AD9545 Evaluation Board

AD9545 Evaluation Board

Features and Benefits

  • Simple power connection using 6V wall adapter and on-board LDO voltage regulators.
  • 10 ac-coupled single-ended (differential signal recombined via a balun) output SMA connectors, with user-configurable output termination for HCSL, CML, or LVDS-compatible (default).
  • 4 configurable reference inputs, selectable between a single ended to differential reference input SMA connector.
  • 1 ac-coupled single-ended input SMA connector for system clock.
  • Pin programmable, power on ready configurability.
  • Status LEDs.
  • USB connection to PC.
  • Microsoft Windows-based evaluation software with simple graphical user interface via an ACE plug-in module
 

Product Detail

The AD9545 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9545 dual digital PLL and 1 pps synchronizer. The AD9545 provides high-precision, multi-output clock generator functions, along with two on-chip jitter cleaning digital PLL cores. PLL0 and PLL1 are optimized for high performance synchronous clocking applications such as GPS, IEEE1588v2, Synchronous Ethernet, OTN, and next generation wireless baseband protocols. The PLLs are fully configurable via serial port control as well as configurable via an external EEPROM for power on ready configurations.

The AD9545 can output up to 5 differential clock signals, plus two single-ended clocks driven by a mix of two high performance digital PLLs, plus two high-precision NCOs (numerically controlled oscillators). 12 total outputs and 4 reference inputs are accessible on the evaluation board.

The output differential transmission line pairs use 50Ω single ended characteristic impedance and are connected to standard edge launch SMA connectors. The AD9545/PCBZ has a fully configurable power supply to allow the user to evaluate the AD9545 while being powered directly by a step down switching regulator or external LDOs. The AD9545 evaluation board uses RoHS-compliant FR-4 material. For convenience, detailed information from the AD9545 data sheet has been included here. Use the user guide in conjunction with the data sheet that has been provided by ADI.

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AD-SYNCHRONA14-EBZ

Multichannel System Clocking Device

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AD-SYNCHRONA14-EBZ

Multichannel System Clocking Device

Multichannel System Clocking Device

Features and Benefits

Processing System

  • Raspberry Pi 4, ARM Cortex-A72, 2GB SDRAM

User Interfaces

  • Gigabit Ethernet
  • 2 × USB 3.0 ports
  • 2 × USB 2.0 ports
  • SPI interface
  • GPIO
  • 2 bicolor LEDs
  • Male pin header

Clock Processing Devices

  • HMC7044 (High Performance, 3.2 GHz, 14-Output Jitter Attenuator)
  • AD9545 (1 PPS Synchronizer and Adaptive Clock Translator)

Clock Outputs

  • 4 x TWINAX LVPECL AC&DC coupled, 100Ω diff
  • 2 x SMA LVPECL AC coupled*
  • 4 x SMA CMOS*
  • 4 x SMA LVDS AC coupled*

*Configurable differential outputs, 50Ω diff

Clock Inputs

  • 3 differential 100Ω SMA clock inputs
  • PPS input
  • SYNC input
  • 10MHz input

Internal references

  • 100Mhz and 122.88Mhz Ultra-Low Phase Noise VCXO's (-165dBc/Hz)
  • 40Mhz and 38.4Mhz TCXO's (±1ppm) 50MHz OCXO(+/- 10ppb)
  • Internal references are software configurable

Power supply

  • DC 12V, 3A barrel jack

Product Detail

The AD-SYNCHRONA14-EBZ is an ideal self-contained device to use in evaluation and prototyping of applications that need a highly accurate frequency and phase-controlled source clock. It is designed around the Analog Devices AD9545 and HMC7044 and greatly simplifies clock distribution and multi-channel synchronization in complex systems. It is intended to be used by trained professionals in a laboratory environment, and not intended as an end product for commercial use. It can be taken as a complete reference design and customised as required for any end customer applications. Full design details are made available free of charge.

The AD-SYNCHRONA14-EBZ comes in a 1U mechanical form factor. Using popular industry connector SMA and TwinAX interfaces most labs will already have the needed cables.

With its internal OCXO it can operate in standalone mode or be fed from a choice of external sources, such as 3 separate high speed differential clock inputs, a 10MHz reference and 1PPS. This flexibility combined with the capability to select either of the internal VCXO options of 100MHz or 122.88MHz, gives almost unlimited choice for the frequency of interest and accuracy needed for a wide variety of application areas. 

APPLICATIONS

  • High accuracy reference clock distribution
  • Systems clocked from a single source
  • Clocks derived from 100MHz or 122.88MHz
  • Phased Array Systems, RADAR, EW, SATCOMS, SDR
  • Bench Equipment
  • Remote controlled operation
Tools & Simulations

Tools & Simulations 1

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