78Q8430
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78Q8430

10/100 Ethernet MAC and PHY

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Adds Ethernet Connectivity with Minimal Impact to Host Processor Utilization

Part Details
Features
  • Single-Chip 10/100 Fast Ethernet Integrated PHY and MAC
  • 32kB SRAM FIFO Memory
    • Adaptive Memory Allocation Between Tx and Rx Paths
    • Queue Independent User-Settable "Watermarks"
    • Per Queue Status Indication
  • Address Resolution Controller (ARC)
    • Multiple Perfect Address Filtering—Eight Default (Max 12)
    • "Wildcard" Address Filtering, Individual, Multicast, and Broadcast Address Recognition and Filtering
    • Positive/Negative Filtering and Promiscuous Mode
  • 64kB JUMBO Packet Support
  • QoS—Four Transmit Priority Levels
  • Non-PCI Pseudo-SRAM Host Bus Interface
    • 8b, 16b, 32b Bus Width
    • Big/Little-Endian Support for 16b/32b Bus Widths
    • Asynchronous (100MHz) and Synchronous (50MHz) Bus Clock Support
  • Low Power and Flexible Power-Supply Management
    • Power-Down/Save, Wake-On LAN (Magic Packet, ON Now Packet), Link Status Change
    • Traffic Offload Engine Functionality
      • Transfer Frame—ARP and ICMP Echo
      • IP Firewall Configuration—Drop Frames on Source IP Address
      • IP Checksum
Additional Details
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The 78Q8430 is a 10/100 Fast Ethernet controller supporting multimedia offload, optimized for host processor offload and throughput enhancements for demanding multimedia applications found in set-top boxes, IP video, and broadband media appliance applications. The 78Q8430 seamlessly interfaces to non-PCI processors through a simplified pseudo-SRAM-like host bus interface supporting 32/16/8-bit data bus widths and provides support for IEEE 802.3x flow control and compliance with IEEE 802.3 and 802.3u standards.

Supporting 10BASE-T and 100BASE-TX, the transceiver provides auto MDI-X cable crossover correction, autonegotiation, link configuration, and full/half-duplex support with full-duplex flow control and requires only a dual 1:1 isolation transformer for line interfacing. Incorporating numerous packet processing and IP address resolution control functions, in addition to an extensive set of error monitoring, reporting and troubleshooting features, the 78Q8430 provides optimal 10/100 Ethernet connectivity in demanding video streaming and mixed-media applications.

Applications

  • Digital Video Recorders/Players
  • High-Definition 1080p/1080i DTVs
  • High-Performance Satellite, Cable, and IPTV Set-Top Boxes
  • IP-PVR and Video Distribution Systems
  • Multimedia Residential Gateways
  • Routers and IADs

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Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 2

78Q8430-ARM9-EVM

78Q8430 ARM9(920T) Embest Evaluation Board User Manual

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78Q8430-ARM9-EVM

78Q8430 ARM9(920T) Embest Evaluation Board User Manual

78Q8430 ARM9(920T) Embest Evaluation Board User Manual

Features and Benefits

  • The system bus interface operates like external memory with an active low chip select.
  • Supports asynchronous big endian bus format.
  • Supports asynchronous 100 MHz operation.
  • Supports 32-bit wide data bus.
  • Optional EEPROM interface for configuration data.
  • Two programmable LED outputs for PHY status.
  • Single +3.3V power supply voltage with a common ground plane.

Product Detail

The 78Q8430 Embest Evaluation Board (78Q8430-ARM9-EVM) is a design example for a 10/100BASE-TX MAC+PHY Embest S3CEB2410 daughter card. The D8430T3A_EB plugs directly into the Embest S3CEB2410 (ARM9™ based) motherboard. The network connection is provided by the 78Q8430 which is a single chip auto-sensing, auto-switching (auto-negotiation or parallel detect modes and auto-MDIX) 10/100BASE-TX Fast Ethernet transceiver with full duplex operation capability. The device is designed specifically for the Audio/Visual (A/V) and Set Top Box (STB) markets and is easily interfaced to available A/V and STB core processors.

The 78Q8430 is compliant with applicable IEEE®-802.3 standards. MAC and PHY configuration and status registers are provided as specified by IEEE802.3u. The integrated MAC is supported by an internal 32KByte transmit and receive SRAM FIFO. The partition of transmit and receive queues is configurable through software, allowing the 78Q8430 to be tuned for specific applications. The device contains hardware support for TCP-IP checksum and ARC address recognition.

Applications

  • Digital Video Recorders/Players
  • High-Definition 1080p/1080i DTVs
  • High-Performance Satellite, Cable, and IPTV Set-Top Boxes
  • IP-PVR and Video Distribution Systems
  • Multimedia Residential Gateways
  • Routers and IADs

78Q8430STEM-DB

78Q8430 STEM Demo Board User Manual

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78Q8430STEM-DB

78Q8430 STEM Demo Board User Manual

78Q8430 STEM Demo Board User Manual

Features and Benefits

  • The system bus interface operates like external memory with an active low chip select.
  • A configurable bus interface with support for little endian and big endian formats.
  • Supports an asynchronous 100 MHz (max) bus clock for STi5100/5514 operation.
  • Supports 32-bit, 16-bit and 8 bit wide data bus formats.
  • Optional EEPROM interface for configuration data.
  • Two programmable LED outputs for PHY status.
  • Single +3.3V power supply voltage with common ground plane.

Product Detail

The 78Q8430 STEM Demo Board (D8430T3B_STEM) is a design example for a 10/100BASE-TX MAC+PHY ST Microelectronics STEM daughter card. The Demo Board plugs directly into STi5100 and STi5514 Evaluation Systems. The network connection is provided by the 78Q8430 which is a single chip auto-sensing, auto-switching (auto-negotiation or parallel detect modes and auto-MDIX) 10/100BASE-TX Fast Ethernet transceiver with full duplex operation capability. The device is designed specifically for the Audio/Visual (A/V) and Set Top Box (STB) markets and is easily interfaced to available A/V and STB core processors.

The 78Q8430 is compliant with applicable IEEE®-802.3 standards. MAC and PHY configuration and status registers are provided as specified by IEEE 802.3u. The integrated MAC is supported by an internal 32KByte transmit and receive SRAM FIFO. The partition of transmit and receive queues are configurable through software, allowing the 78Q8430 to be tuned for specific applications. The device contains hardware support for TCP-IP checksum and ARC address recognition.

Applications

  • Digital Video Recorders/Players
  • High-Definition 1080p/1080i DTVs
  • High-Performance Satellite, Cable, and IPTV Set-Top Boxes
  • IP-PVR and Video Distribution Systems
  • Multimedia Residential Gateways
  • Routers and IADs

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