Features and Benefits

  • Library provides an inbuilt adaptive jitter buffer for re-sequencing and jitter abstraction
  • Supports encapsulation of telephony events into RTP packets
  • Supports telephony tones
  • Supports comfort noise
  • Supports redundant audio.
  • Library supports concurrent payloads
  • Target Processor: Code compatible across the Blackfin Processor Family ADSP-BF5xx
  • Release format: Object code module with C source wrapper
  • Input format: Packet or payload depending on parsing or assembling
  • Input buffer samples per block: User-configurable
  • Framework dependencies: None
  • Output format: Payload or packet depending on parsing or assembling
  • Sample Rate: 8 kHZ
  • Multi-threading: Fully re-entrant and multi-instancing capable

Product Details

The RTP/RTCP stack is widely used as the data transport protocol in real-time network services such as Voice over Internet Protocol (VoIP) applications. The use of the packet switched network for voice increases bandwidth utilization compared with the traditional connection-oriented approach and can lead to lower call costs. The nature of packet   switched networks can cause unpredictable and variable delays to speech packets, often resulting in poor unintelligible speech at the receiving end. The effect due to these delay variations or jitter can be minimized by using a Jitter Buffer, which imposes a certain delay to each packet before playing back the packet stream at a constant rate. The library provides an integrated jitter buffer to counter the same along with RTP/RTCP module.


Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.

Performance Metrics

 MIPS summary:

Code memory (KiB)
Data RAM (KiB)  Constant Data Tables (KiB)   MIPS Average

  • MIPS measured for specified payload using optimal memory layout running on a BF561 processor.
  • Code compatible across all BF5xx processors, with silicon anomaly workarounds implemented based on BF533 Silicon Revision 0.3 and later.
  • "Data RAM" for one instance, includes Scratch, Instance/State, Heap, Minimum Input and Output Single Buffers. The above measurement is with maxpool=1.
  • 1 KiB = 1024 Bytes.
  • BF533, BF561, BF518 and BF561 supported.

Systems Requirements

  • Windows XP Professional SP3 (32-bit only).
  • Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
  • Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.
  • Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
  • Minimum of 1 GB memory (RAM), 4 GB is recommended.
  • Minimum of 2 GB hard disk (HDD) space is required.

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