Electrification & Powertrain

This circuit uses the ADuCM360/ADuCM361 precision analog microcontroller in an accurate thermocouple temperature monitoring application. The ADuCM360/ADuCM361 integrates dual 24-bit sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), dual programmable current sources, a 12-bit digital-to-analog converter (DAC), and a 1.2 V internal reference, as well as an ARM Cortex-M3 core, 128 kB flash, 8 kB SRAM, and various digital peripherals such as UART, timers, SPIs, and I²C interfaces.

In the circuit, the ADuCM360/ADuCM361 is connected to a thermocouple and a 100 Ω platinum resistance temperature detector (RTD). The RTD is used for cold junction compensation.

In the source code, an ADC sampling rate of 4 Hz is chosen. When the ADC input programmable gain amplifier (PGA) is configured for a gain of 32, the noise-free code resolution of the ADuCM360/ADuCM361 is greater than 18 bits.

This circuit uses the ADuC7060 or the ADuC7061 precision analog microcontroller in an accurate thermocouple temperature monitoring application. The ADuC7060/ADuC7061 integrate dual 24-bit sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), dual programmable current sources, a 14-bit digital-to-analog converter (DAC), and a 1.2 V internal reference, as well as an ARM7 core, 32 kB flash, 4 kB SRAM, and various digital peripherals such as UART, timers, serial peripheral interface (SPI), and I²C interfaces.

In the circuit, the ADuC7060/ADuC7061 are connected to a thermocouple and a 100 Ω platinum resistance temperature detector (RTD). The RTD is used for cold junction compensation. As an extra option, the ADT7311 digital temperature sensor can be used to measure the cold junction temperature instead of the RTD.

In the source code, an ADC sampling rate of 4 Hz was chosen. When the ADC input programmable gain amplifier (PGA) is configured for a gain of 32, the noise-free code resolution of the ADuC7060/ADuC7061 is greater than 18 bits.

The single edge nibble transmission (SENT) interface to the host is implemented by using a timer to control a digital output pin. This digital output pin is then level shifted externally to 5 V using an external NPN transistor. An EMC filter is provided on the SENT output circuit as recommended in Section 6.3.1 of the SENT protocol (SAE J2716 Standard). The data is measured as falling edge to falling edge, and the duration of each pulse is related to the number of system clock ticks. The system clock rate is determined by measuring the SYNC pulse. The SYNC pulse is transmitted at the start of every packet. More details are provided in the SENT Interface section.