Read-Channel Processor Uses PRML to Increase Capacity of MR Head-Based Disk Drives

The computing world's insatiable appetite for storage capacity continues unabated as new operating systems-such as Windows 95-applications suites, and multimedia become universally accepted. Typical PC systems are now shipped with hard-disk drives (HDD) capable of storing from 640 MB to 1 GB of information, compared with 340-540 MB in 1994 and 200- 300 MB in '93. As the "home PC" has gained acceptance worldwide, HDD unit shipments were pushed to nearly 70 million in 1994 and are expected to exceed 100 million by 1997.

The ongoing challenge for HDD manufacturers is to provide a continuous stream of new products that improve storage capacity at the same (or lower) cost. The principal method of providing a drive that offers both higher capacity and lower cost is to increase storage capacity by increasing areal density per platter. Historically, areal density has been improved at the rate of about 30% per year. Recently, however, industry leaders are transitioning to a new trend line improving the rate of increase to over 60% per year.

A variety of techniques and technologies are employed by the HDD designer to meet areal density objectives: improvements in media, head technology, recording modulation, and head-positioning tolerances. This article discusses the key factor of recording modulation technique and how it is matched to the type of head being used in the system. The recording modulation / demodulation in a disk drive is implemented by the "read-channel processor".

What a read-channel processor is and what it does:

The read-channel processor can be looked at as a sophisticated analog-to-digital converter that translates weak analog signals (representing digital information) from a disk drive head to a digital bit stream. In just the past few years the signal processing functions that are included in a read-channel IC have significantly increased in performance and complexity, using partial-response, maximum-likelihood (PRML) architecture. PRML bridges the gap between traditional peak-detect pulse extraction and higher performance maximum-likelihood signal-detection schemes employed in communications systems, including modems, digital VCRs, etc.¹

In a disk drive application the "communication channel" includes:

  • A transmitter that transforms binary (0,1) user data into polarity changes of the current in a magnetic coil (write head).
  • A transmission channel, consisting of a magnetic disk that stores information as changes in the direction of magnetization.
  • A receiver that reads the analog signal from the disk and processes it to recover the original binary data.

In today's disk drives, the read-channel processor implements the intelligent transmitter/receiver functions-not including the transducer (write head, write driver electronics) and sensor (read head, read preamplifier) circuitry.

Pulse identification problem:

Magnetic transitions on the disk are transformed into voltage pulses with alternating polarity at the output of the read head sensor. An isolated transition in the read channel (which corresponds to a step change in the magnetization) can be approximated by the Lorentzian pulse (Figure 1), given by:

Equation 1

where PW50 is the time between the points at which the amplitude is 50% of its peak value. The signal peaks as the magnetization changes direction.The data rate at which the user is able to transfer information through the read/write channel can be characterized by the time interval between user bits "T". For a given pulse width, the goal is to pack bits closer, i.e., to increase the PW50/T ratio, which is referred to as user bit density.

Peak detection vs. PRML:

Figure 1

At lower bit densities, where the interaction between adjacent pulses is relatively small, the receiver can be implemented with a peak detector (see Analog Dialogue 22-1, 1988). Peaks representing binary "ones" in the read-back signal are detected by operating on the signal with a differentiator, followed by a zero-crossing comparator. The comparator output is gated by an amplitude qualification circuit that disables the digital output pulse when the input read signal amplitude is below a certain threshold value.

A peak detector's operation is continuous in time, and is driven by the input signal only. The industry's first fully integrated "peak-detect" read channel was introduced by Analog Devices with the AD899 family of products.² Peak detection is still in use for reading servo information (in head positioning), as a servo data qualifier in some present day products.

But as the storage density is increased, the increased interaction between adjacent pulses of opposite polarity produces destructive interference. For a peak detector to operate correctly (i.e., with a low bit error rate) this inter-symbol interference (ISI) and the resulting amplitude decrease and peak shift have to be eliminated. In contrast, partial response (PR) signaling (in which each pulse in a neighborhood contributes partially in the process of determining the presence or absence of a pulse in a given location) accepts a controlled amount of interference (cancellation) between neighboring pulses. The most likely (ML = maximum likelihood) series of pulses is continually updated, using discrete-time (sampled) signal-processing techniques.

In the various classes and orders of partial-response channels the amount of inter-symbol interference (signal cancellation) is chosen so that only a finite set of discrete amplitudes is generated at the sampling instances when adjacent pulses interfere. In PR4 signalling, which allows the existence of +1, 0, -1 nominal sample values, the isolated pulse is shaped (by continuous and discrete time filters) and the sampling clock phase is adjusted so that only two +1, +1 or -1, -1 sampled values are received; at all other times the samples are zero.

When two magnetic transitions on the disk are at the closest, the corresponding read-back samples (+1, -1) partially cancel, and the resulting sampling of adjacent pulse values is +1, 0, -1. (One could say that each of the transitions is partially responsible for the 0 sample in the middle.) In higher-order partial response systems, like Enhanced PR4 (EPR4), pulse responses due to more than two transitions are allowed to interfere, generating a larger number of possible sample values (e.g., +2, 1, 0, -1, -2, for the EPR4 case).

MR heads:

Besides the storage density improvements resulting from the application of sophisticated signal processing techniques, the staggering rate of increase of disk-drive capacity is largely due to the use of magnetoresistive (MR) read heads which are quickly replacing their inductive counterparts. To date, more than 50 million MR heads have been produced, and that number will likely be equalled this year.

MR read heads employ the principle of anisotropic magnetoresistance (AMR) to convert magnetic field variations of 5 A/m (oersteds) to about a 2.5% change in resistance. In addition, research continues on GMR (giant MR) which yields 5 times the sensitivity of AMR. This allows drive designers to pack more bits into a given surface area, or to relax other design constraints to increase performance elsewhere. [note: even before GMR is implemented in production drives, development of CMR (colossal MR) is well under way; CMR holds the promise of very dramatic improvement over GMR.] The sensor itself is a thin film (about 250 ) of Ni-Fe (nickel iron), also called permalloy, and is just a few µm on each side. Modulation in the resistance of the MR element appears as a differential voltage swing at the output of the preamplifier (20-200 mV peak to peak); it is then ac-coupled to the read channel processor inputs (Figure 2).

Figure 3

MR-head asymmetry:

MR head technology solves numerous problems associated with inductive heads, such as the dependence of signal amplitude from the platter on its rotational speed. But MR heads have created many new challenges for disk drive designers. One of the problems is the change in resistivity when, occasionally, the MR head touches the disk surface. This contact causes a sudden rise in temperature, resulting in a long-lasting (about 10 µs) voltage transient; to the read channel it appears as a large dc offset with a long tail.

Another issue of concern is the asymmetrical nonlinear transfer function of the MR sensor) due to biasing and the head's off-track position. The asymmetrical read waveform impairs both servo and read channel performance. Furthermore, ac coupling of an asymmetrical signal compounds the problem by introducing dc offset and/or pattern-dependent baseline shift and transients.

By considering MR head-related problems in the design of the read-channel chip, semiconductor vendors like Analog Devices can add significant value to the disk-drive electronics. This is exemplified in the ADRS1xx family.

Product features:

Parts in the ADRS1xx family are available with a variety of signal-processing functions and options. They offer a complete signal-processing solution for state-of-the-art disk drives, especially when MR technology is combined with PRML processing. The circuit blocks are implemented in CMOS, which permits timely delivery of cost-effective semicustom chips.

Figure 3 is a block diagram of a typical ADRS1xx read-channel chip. An assortment of continuous and discrete time filters realize the necessary combination of low-pass noise filtering and frequency boost for pulse slimming. A 7th order equiripple filter with two independently programmable zeros, in combination with an analog or digital 5-tap, adaptive FIR filter, carries out low-pass filtering and equalization of the read-back signal to a PR4 target. The option of shaping the analog signal in the sampled analog domain, before the quantization process takes place, can eliminate the enhancement of quantization noise and reduces the effective number of bits (ENOB) required in the A/D converter.

A patented dual analog/digital automatic gain control (AGC) loop in tandem with a hybrid phase locked loop (H-PLL) take care of adjusting both the amplitude and the sampling instance of the read signal. Gain switching during acquisition and tracking with programmable damping factor in the PLL assures easy optimization of the loop dynamics. In addition, the use of active offset cancellation in the analog front end, together with a user-activated clamping function (time constant reduction of the AC coupling networks), can significantly shorten the recovery time from offset transients (thermal asperity).

A/D Converter:

The ADC is a full-flash type, 6-bit, 144-MSPS (megasamples per second), with built-in patented MR head asymmetry correction. The MR head asymmetry is eliminated using the ADC's gain correction and/or dc offset correction; each ADRS1xx provides registers to store user-programmed correction code. In larger disk drives with multiple platters-and multiple MR heads-correction code for each platter is stored on the drive for on-the-fly switching.

Figure 3

PR4 and EPR4 Viterbi detectors implement maximum likelihood detection (PRML). Unlike peak detectors that make consecutive irrevocable decisions, bit by bit, as to whether a peak was greater than a certain fixed threshold, maximum likelihood detectors compare sequences of signal samples to all possible combinations and pick the one that matches the received signal sequence the best. Viterbi detectors perform maximum likelihood detection in a recursive fashion, i.e., by executing some of the computation at every "bit time". A set of threshold values are dynamically adjusted, based on previous signal samples, and compared to the latest signal sample (US patent 5,373,400).

Each of these tentative (soft) decisions can and will be modified at a later time (within limits of the available memory) if additional signal samples indicate that a previous decision was wrong.

Evaluation board with Windows Software:

Lab experiments and characterization of the part are simplified by the availability of an evaluation kit. The kit includes National Instruments' LabView®-based software for evaluating the ADRS120 with either a spin stand or on a stand-alone basis. The evaluation board plugs into the parallel port of a 486 (or Pentium class) PC running Windows. The board provides all the components necessary to operate any member of the ADRS1xx family.

Figure 4


  1. See "A high-density recording technology for digitalVCRs, by Keiji Kanota et al, 1990. IEEE Transactions on Consumer Electronics, volume 36, no. 3.
  2. See Analog Dialogue 26-2, pp. 21-22. See also Conference Record for 1992 IEEE ISSCC: Kovacs, J. and W. Palmer, "A 32-Mb/s fully integrated Read channel for disk drive applications."



Janos Kovacs


Ron Kroesen


Al Haun