The LT1943 is a highly integrated, four-output switching regulator designed to power large TFT Liquid Crystal Displays (LCDs). The first step-down switching regulator provides a logic voltage with up to 2A of current. The other three regulators are a high-power boost regulator, a low-power boost regulator and an inverting regulator, which provide the three bias voltages, AVDD, VON and VOFF, required by LCDs. Switching regulators are chosen over linear regulators to accommodate a wide input voltage range (providing both step up and step down functions) and to minimize power dissipation. The LT1943’s wide input range, 4.5V to 22V, allows it to accept a variety of power sources, including the commonly used 5V, 12V and 19V rails. The low-profile 28-pin TSSOP package has an exposed metal pad on the backside to maximize thermal performance.
All of the regulators are synchronized to a 1.2MHz internal clock, allowing the use of small, low cost inductors and ceramic capacitors. Since different types of panels may require different bias voltages, all output voltages are adjustable for maximum flexibility. Programmable soft-start capability is included in each of the regulators to limit inrush current.
Figure 1 shows a 4-output TFT LCD power supply with 8V to 20V input voltage range. The first output provides a 3.3V, up to 2A, logic supply using a buck regulator. The second output employs a SEPIC converter to generate a 13V, 500mA AVDD bias supply. Another boost converter and an inverter generate VON and VOFF.
When power is first applied to the input, the RUN-SS capacitor starts charging. When its voltage reaches 0.7V, switcher one is enabled. The capacitor at RUN-SS pin controls the ramp-rate for the Switcher 1 output, VLOGIC and inrush current in L1. Switchers 2, 3 and 4 are controlled by the BIAS pin, which is usually connected to VLOGIC. When the BIAS pin is higher than 2.8V, the capacitor at the SS-234 pin begins charging to enable switchers 2, 3 and 4. When AVDD reaches 90% of its programmed voltage, the PGOOD pin is pulled low.
When AVDD, VOFF and E3 all reach 90% or their programmed voltages, the CT timer is enabled and a 20µA current source begins to charge CT. When the CT pin reaches 1.1V, the output PNP turns on, connecting E3 to VON. Figure 2 shows the start-up sequence of the circuit in Figure 1.
If one of the regulated voltages, VLOGIC, AVDD, VOFF or E3 dips more than 10%, the internal PNP turns off to shut down VON . This action protects the panels, as VON must be present to turn on the TFT display. Each regulator has a frequency foldback oscillator, which reduces the switching frequency to 250kHz when its FB pin is at 0V. This frequency foldback feature reduces the average inductor current during start-up and overload conditions, minimizing the power dissipation in the power switches and external components. It also helps the short-circuit protection for the Buck and SEPIC regulators. The overall efficiency is shown in Figure 3. The converter uses all ceramic capacitors, with X5R and X7R types recommended, as these materials maintain capacitance over a wide temperature range.
If the input voltage is 5V, a boost regulator can be used in place of the SEPIC to generate the AVDD supply. With the higher efficiency of the boost topology and lower input voltage, the overall circuit efficiency increases to 90%. The PGOOD pin can drive an optional PMOS device at the output of the boost regulator to disconnect the load from the input during shutdown.
Careful PC board layout is important for proper operation. Paths that carry high switching current should be short and wide to minimize parasitic inductance. In a buck regulator, this loop includes the input capacitor, internal power switch and Schottky diode. In a boost regulator, this loop includes the output capacitor, internal power switch and Schottky diode. In a SEPIC converter, this loop includes the internal power switch, flying capacitor, Schottky diode and the output capacitor. Keep all the loop compensation components and feedback resistors away from the high switching current paths. The LT1943 pinout was designed to facilitate PCB layout. Use a separate ground trace to connect the ground return of the compensation components and bottom feedback resistors to the signal ground (SGND pin). Connect the SGND to the power ground on the backside of the IC. Keep the traces from the center of the feedback resistors to the corresponding FB pins as short as possible. LT1943 has an exposed ground pad on the backside of the IC to reduce thermal resistance. A ground plane with multiple vias into ground layers should be placed underneath and near the part to conduct heat away from the IC.
The LT1943 provides compact power supply solutions for TFT-LCD panels. All four outputs come from switching regulators for wide input voltage range and minimum power dissipation. All four circuits use only ceramic capacitors to minimize ripple, size and cost.