Get a 3dB SNR Boost Using a Dual ADC

Using a dual channel simultaneous sampling ADC and some simple averaging techniques, the SNR of the converter can be improved by 3dB.

Step 1. Collect data using both channels of the ADC using symmetrical input networks as shown below in Figure 1.

Get a 3dB SNR Boost Using a Dual ADC
Figure 1. LTC6409 Driving Dual Channel LTC2185

This example uses the LTC2185 ADC and the LTC6409 amplifier. There is a single-ended 10MHz low pass filter (LPF) before the amplifier and a simple LPF after the amplifier.  R1 and R2 are driven by the same signal source.

Step 2. Collect the data in an FPGA. Since a dual ADC like the LTC2185 is simultaneously sampling, the two channels will align in the digital domain and they can easily be manipulated.

Step 3. Sum the two channels in the digital domain. Because these signals are simultaneously sampled the data can be summed point for point in the digital domain. 

Here is an example:

Get a 3dB SNR Boost Using a Dual ADC
Table 1. Data From Dual Channel ADC

Once these data points are summed they can then be subject to the remaining digital signal processing of the application. The result will be a 3dB improvement in SNR.


FFT data from both channels individually:

Get a 3dB SNR Boost Using a Dual ADC
Figure 2. FFT Data From Both Channels Individually

FFT data after summation:

Get a 3dB SNR Boost Using a Dual ADC
Figure 3. FFT Data After Summation

Why this works?

This technique is possible because when coherent signals (signals with the same phase, frequency and amplitude characteristics) are summed they sum in terms of voltage. But random signals like noise which are phase-, frequency- and amplitude-independent only sum in terms of power. So the signal of interest will increase by 6dB after summation, and the noise will only increase by 3dB after summation. This will give a net increase in SNR of 3dB. In reality there will be some shared jitter between the two channels that will be coherent, so the actual SNR gain is slightly less than 3dB.



Clarence Mayott

Clarence Mayott is a mixed signal application section leader with over 10 years of experience at Linear Technology.

Beginning with the DC1151, a demo board for the LTC2246H, Clarence has designed nearly all of the high speed ADC demo boards for Linear Technology. These boards have been used for evaluation purposes in a wide range of applications. He designed demo boards with complete signal chains combining amplifiers and ADC combinations to help the end customer evaluate systems more easily. He also designed companion boards, including clock and signal source boards, to help facilitate the evaluation of high speed ADC demo boards. Clarence manages the continued development of PScope, the software used for various pipeline and SAR ADCs.

His expertise in design and layout of demo boards allows him to instruct customers on how to implement high speed ADCs into their own designs. He has worked on many technical areas, including medical, automotive and communications. His experience allows him to see schematic errors, minute layout errors, and other design flaws in designs.

With the release of the LTC2000, Clarence has expanded his knowledge base to include high speed DACs and waveform generation in addition to high speed ADCs. As an application section leader he oversees the continued development of LTDACGen a new software tool for generating complex waveforms for high speed DACs.

He has given technical trainings both within Linear Technology and to potential customers describing how to implement proper signal chains from the antenna through the FPGA.

He received an M.S. in Electrical Engineering from Santa Clara University and a B.S. degree in Electrical Engineering from California State University Polytechnic San Luis Obispo.