# Online Simulator Validates Buck Converter Output Error Budget Analysis

## Author's Contact Information

### Abstract

A predictive buck converter output voltage accuracy depends in part on the estimated amplitude of the transient response to a load current step. The amplitude of the buck converter droop under load is estimated with back-of-the-envelope calculations and with Maxim's online EE-Sim® DC-DC Converter Design Tool, testing different ways to perform the estimate and their associated level of accuracy.

### Introduction

We need to perform an output voltage error budget analysis for one of our buck converter designs. The biggest contributor to the error is the output droop consequent to the load step. Having tried different methods to estimate the droop has led to different results. How do we make sense of it? In this design solution, we perform a buck converter output error budget analysis. In estimating the droop amplitude, we compare a simulated result with two different back-of-the-envelope estimates and reconcile the different approaches.

### The Error Budget

For this calculation, the buck converter parameters of interest are:

VIN = 5V, VOUT = 3.3V

VOUT DC accuracy µ2% = µ66mV

The other defining elements of the buck converter are:

Clock frequency = 695kHz

L = 2.7µH, C = 2 x 22µF

The design for this buck converter is created with the online EE-Sim DC-DC Converter Design Tool. Simulation results provided by this tool indicate the following:

VOUT ripple = 2.6mVP-P or ≈ ±1.3mV (Figure 1)

VOUT transient droop from 1A to 2A = 157mV (Figure 2)

Accordingly, the estimated worse-case error budget (negative deviation of the output voltage) is:

VERROR = 66 + 157 + 1.3 = 224.3mV

The given target error budget is 240mV against an estimated error of 224.3mV. All is well, but why is the result not in line with our back-of-the-envelope calculations?

### CdV/dt Back-of-the-Envelope Estimate

A formula often used for this calculation is:

Where I is the load step (1A), C is the output capacitor (2 × 22µF), and fBW is the regulator closed-loop bandwidth. For the closed-loop bandwidth, fBW, one can take a fraction of the clock frequency as a set value. In Figure 3, we have the luxury of an online simulation (18.8kHz).

The rationale for this formula is that if the load step is steep the capacitors takes all the hit, linearly discharging according to the law:

Where t is the discharge time. The capacitor’s discharge lasts until the loop responds after a delay proportional to the inverse of the closed-loop bandwidth, fBW:

By substitution of equation (3) into equation (2), we get equation (1). With this formula, the estimated droop is:

Note that an unusual capacitance value, 44.6µF, is used. This is because high-density ceramic capacitors have capacitance that can vary dramatically with applied voltage. We use the actual capacitance with a bias of VOUT (3.3V) based on data provided by the device manufacturer and used by the EE-Sim design tool. This leads to a total error of:

VERROR = 66 + 190 + 1.3 = 257.3mV

257.3mV is above the 240mV budget. This is the estimate we are concerned about. At first, the rationale for the formula appears to be sound, but what is wrong with it?

### LC Resonant Back-of-the-Envelope Estimate

The first thing we notice is that the formula completely neglects the presence of the inductor (2.7µH). During the time the loop is unresponsive, the output is essentially an LC resonant circuit as shown in Figure 4 (a SIMPLIS® simulation).

In this case, the circuit tends to develop an oscillation of amplitude:

v = ZI sin? 2π × fRES × t

Where t is time, I is the 1A load step and:

Naturally, this oscillation unfolds only until the loop responds after a delay time t given by equation (3). Accordingly, the sinusoid will stop at:

With the inductor back in the picture, the estimated droop value is 171mV, much closer to the simulated 157mV. With a 171mV droop estimate, the error is 238.3mV, still within the 240mV budget.

### Reconciliation

Short of simulating it or building the circuit and exercising it with a current load step generator, we can find the first-order estimate of the droop amplitude with two formulas, one for the linearized droop model:

and another with the resonant model:

Which one should be used in lieu of a full-fledged simulation or breadboard construction? As often is the case, it depends. If your fRES << fBW, then by using the approximation sin x ≈ x in VdroopLC, we have:

And by substituting Z and fRES with their expressions, we have:

For fRES << fBW, either expression works. Figure 5 shows the difference between the two approaches and the linearization error.

In our case, the two frequencies are pretty close and so the CdV/dt-based approximation fails.

### The Simulation Advantage

The EE-Sim design tool uses SIMPLIS to simulate the performance of a circuit. SIMPLIS was developed and optimized for simulating switching circuits like DC-DC converters. Unlike our simple back-of-the-envelope calculations, a simulation takes into account all the factors of the circuit, or at least those that are in the component models. Naturally, our hand calculations are crude estimates with simplified equations that do not include all the effects of the circuit and neglect the component parasitics (e.g., ESR, etc.). Hence, the simulation provides the most accurate results.

### Conclusion

We performed an output voltage error budget analysis for the MAX17242  buck converter design. We simulated the ripple and load step voltage droop amplitude contributions to the error using the EE-Sim online DC-DC tool. Our initial hand calculations of the voltage droop appeared to be pessimistic compared to the simulations. We reviewed our assumptions and developed a more accurate back-of-the-envelope approach to the step-response calculation. The result from this approach came much closer to the simulated result. This, and more importantly the simulation result, eased our initial concerns about the ability to meet the error budget.