MAXREFDES1013

The MAX17595 is a peak-current-mode controller for designing wide input-voltage flyback regulators. The MAX17595 offers optimized input thresholds for universal input AC-DC converters and telecom DC-DC (36V to 72V input range) power supplies. It contains a built-in gate driver for an external n-channel MOSFET. The MAX17595 houses an internal error amplifier with 1% accurate reference, eliminating the need for an external reference. The switching frequency is programmable from 100kHz to 1MHz with an accuracy of 8%, allowing optimization of magnetic and filter components, resulting in compact and cost-effective power conversion. For EMI-sensitive applications, the MAX17595 incorporates a programmable frequency dithering scheme, enabling low-EMI spread-spectrum operation. Users can start the power supply precisely at the desired input voltage, implement input overvoltage protection, and program soft-start time. A programmable slope compensation scheme is provided to ensure stability of the peak current-mode control scheme. Hiccup-mode overcurrent protection and thermal shutdown are provided to minimize dissipation in overcurrent and overtemperature fault conditions.

• Programmable Switching Frequency Allows Optimization of the Magnetic and Filter Components, Resulting in Compact, Cost-Effective, Efficient Isolated/ Nonisolated Power Supplies
• 100kHz to 1MHz Programmable Switching Frequency with Optional Synchronization
• Peak Current Mode Control Provides Excellent Transient Response—Offline (Universal Input AC) and Telecom (36V to 72V) Flyback Controller
• Programmable Frequency Dithering Enables Low EMI Spread-Spectrum Operation
• Integrated Protection Features Enhance System Reliability
• Adjustable Current Limit with External Current Sense Resistor
• Fast Cycle-By-Cycle Peak Current Limiting Hiccup-Mode Short-Circuit Protection
• Overtemperature Protection
• Programmable Soft-Start and Slope Compensation
• Input Overvoltage Protection

An offline DCM flyback converter using the MAX17595 is demonstrated for a 24V DC output application. The power supply delivers up to 0.5A at 24V. Table 1 shows an overview of the design specification.

This document describes the hardware shown in Figure 1. It provides a detailed systematic technical guide to designing an offline discontinuous conduction mode (DCM) flyback using Maxim’s MAX17595 current-mode controller. The power supply has been built and tested, details of which follow later in this document.

Figure 2 shows a generic isolated power-supply block diagram. It consists of a power stage, an isolation transformer, rectifier, secondary-side error amplifier, and opto-coupler to provide a feedback for the primary side control. Different isolated power supplies are different depending upon how the transformer is being used in them.

A transformer in a flyback configuration acts differently than its usual operation of transformation of energy from primary to secondary. During a transformer’s usual operation, both primary and secondary windings conduct together at the same time to make the transfer of energy possible from primary to secondary. In a flyback configuration the primary and secondary windings do not conduct at the same time and the transformer acts more like a coupled inductor. Note that in this document we have used the following notations for the transformer turns ratio:

This means capital K for primary turns/secondary turns and small k for secondary turns/primary turns.

Figure 3 shows a simple flyback topology that consists of a transformer whose primary winding is connected to the drain of a switching MOSFET. The source of the MOSFET is connected to ground. The secondary winding is connected to the output capacitor through a rectifier diode. In this flyback configuration the current flows into the primary winding during the on time of the switching period and flows into the secondary winding during the off time of the switching period.

During the on-time when the primary switch is closed, a current, I_P, flows through the primary winding as shown in Figure 4. I_P can be written as follows:

The peak magnitude of the primary current can be written as follows:

In the secondary winding, a negative voltage is induced due to the current flowing in to the primary. The rectifier diode is reverse-biased and no current is flowing in the secondary winding. The induced voltage in the primary can be written as:

During the off-time when the primary switch opens as shown in Figure 5, the magnetic field in the primary winding collapses and the voltage at the winding reverses, while current keeps flowing in the same direction until the field fades away.

The secondary current I_S flows and the secondary and rectifier diode is forward-biased. Output voltage V_OUT is now available across the secondary coil if we ignore the forward voltage drop of the rectifier diode. The secondary winding voltage is now flown away to primary side as K x V_OUT. This voltage is present across the switch until the current in the secondary winding decays to zero. Total voltage available across the switch during the off-time can be written as:

V_SW = V_IN + K x V_OUT

This voltage also causes the breakdown of the magnetic flux in the primary winding (no current is flowing in the primary winding after this reset). Here we can see that unlike a usual transformer action where current flows in both the winding at the same time, in a flyback transformer the current flows into the primary winding during the on-time and into the secondary winding during the off-time. This is why we use the term “coupled storage inductor” for transformers used in flyback operation. It should be noted though that mechanically these transformers are like any transformer. Use in flyback operations makes transformers act differently as coupled inductors. The required duty cycle for a given input voltage and output voltage can be calculated from:

where:

Figure 6 shows a typical CCM mode flyback primary and secondary winding current, and Figure 7 shows a typical DCM mode flyback waveform.

Now that the basic principle of the DCM flyback is understood, a practical design can be illustrated. The design parameters are obtained by using expressions given in Application Note 5504. This document is primarily concerned with the power stage and the feedback loop design, and is intended to complement the information contained in the MAX17595 data sheet.

Flyback converters can be operated in discontinuous conduction mode (DCM) or continuous conduction mode (CCM). The component choices, stress level in power devices, and controller design vary depending on the operating mode of the converter. The design discussed in this document is a DCM design and expressions for calculating component values and ratings are presented to achieve the design goals.

Step 1: Switching Frequency

For offline flyback operation, the selection of switching frequency is of prime importance. Thermal limits and junction temperature of the device limits the selected switching frequency to be less than 150kHz. For this design we have selected a switching frequency of 140kHz. The MAX17595 switching frequency is programmable between 100kHz and 1000kHz with a resistor R_RT connected between RT and SGND. The R_RT is calculated as follows:

A standard 71.5kΩ resistor is selected for R_RT.

Step 2: Transformer Magnetizing Inductance and Turns Ratio

In a DCM flyback converter, the energy stored in the primary inductance of the flyback transformer is delivered entirely to the output. The maximum primary-inductance value for which the converter remains in DCM at all operating conditions can be calculated as:

where:

D_MAX = 0.43V

V_D = 0.7V is the forward voltage drop of the rectifier diode of the secondary winding.

In this offline application, the DC bus voltage varies from 282V DC to 340V DC. But the actual minimum input operating voltage depends on the 100Hz ripple present on the DC bus capacitor. In this application, the ripple is assumed to be 70.71V (25% of V_INMIN) and hence the minimum DC input to the converter.

V_INMIN = 200 x √2 − 70 = 212.13V

Substituting the above values in the expression of L_MAG as follows:

To account for 10% tolerance in primary inductance for our design, L_MAG is chosen as 1750µH, L_PRI = 1750µH.

The leakage inductance of the transformer should be targeted as low as possible. For this design, we achieved a 1% leakage inductance of 17.5µH, L_LKG = 17.5µH.

A customized transformer 750316881 from Würth Electronik is used in this design. This transformer also fulfills the specification of turns ratio, bias winding, and primary/secondary currents requirement of the design that is calculated step by step in this document. The transformer has dielectric isolation specification of 3900V AC.

Step 3: Maximum Duty Cycle Calculation with Selected L_PRI

Use the following expressions to calculate the maximum duty cycle of the converter for the selected frequency and magnetizing inductance:

Calculate the required transformer turns ratio (k) using the expressions as follows:

For the present design, k is chosen as 1:0.1717.

Step 4: Calculation of Peak/RMS Current

Primary and secondary RMS and primary peak currents calculations are needed to design the transformer in switched-mode power supplies. Also, primary peak current is used in setting the current limit. Use the following expressions to calculate the primary and secondary peak and RMS currents.

Step 5: Current Limit Resistor Calculation

For current limit setting, the peak current can be calculated as follows:

I_LIM = 1.2 x I_PRIPEAK = 1.2 x 0.35 = 0.4199A

The devices include a robust overcurrent protection scheme that protects the device under overload and short-circuit conditions. A current-sense resistor, connected between the source of the MOSFET and PGND, sets the peak current limit. The current-limit comparator has a voltage trip level (V_CS-PEAK) of 300mV. Use the following equation to calculate the value of R_CS:

where I_MOSFET is the peak current flowing through the MOSFET. A typical 750mΩ current-sense resistor is selected, R_CS = 750mΩ.

Step 6: MOSFET Selection

MOSFET selection criteria includes maximum drain voltage, peak/RMS current in the primary, and the maximum allowable power dissipation of the package without exceeding the junction temperature limits. The voltage seen by the MOSFET drain is the sum of the input voltage, the reflected secondary voltage on the transformer primary, and the leakage inductance spike. The MOSFET’s absolute maximum V_DS rating must be higher than the worst-case drain voltage as follows:

For this application, the 800V 11A n-channel MOSFET STB11NM80T4 from ST Micro is selected as the primary MOSFET.

Step 7: Snubber Selection

Ideally, the external MOSFET experiences a drain-source voltage stress equal to the sum of the input voltage and reflected voltage across the primary winding during the off period of the MOSFET. In practice, parasitic inductors and capacitors in the circuit, such as leakage inductance of the flyback transformer, cause voltage overshoot and ringing in addition to the ideally expected voltage stress. Snubber circuits are used to limit the voltage overshoots to safe levels within the voltage rating of the external MOSFET. The snubber capacitor can be calculated using the following expression:

Considering the derating of the capacitor, we selected a capacitor of value 470pF, C_SNUB = 470pF.

The power that must be dissipated in the snubber resistor is calculated using the following expressions:

P_SNUB = 0.833 x L_LKG x I_PRIPEAK2 x f_SW

P_SNUB = 0.833 x 17.5µ x 0.352 x 140k = 0.25W

The snubber resistor is calculated based on the below expression:

A standard resistor of 499kΩ 0.4W is selected, R_SNUB = 499kΩ.

The voltage rating of the snubber diode is:

An 800V, 1A diode US1K-TP from Micro Commercial Components is selected as the snubber diode for this design.

Step 8: Selection of Secondary Diode

The maximum operating reverse-voltage rating of the secondary rectifier diode must be higher than the sum of the output voltage and the reflected input voltage. We use the following expression to calculate the secondary diode voltage rating:

V_SEC,DIODE = 1.25 x (k x V_INMAX + V_OUT)

V_SEC,DIODE = 1.25 x (0.1717 x 339.4 + 24) = 102.8V

The current rating of the secondary diode should be selected so that the power loss in the diode (given as the product of forward-voltage drop and the average diode current) should be low enough to ensure that the junction temperature is within limits. It is recommended to select fast-recovery diodes with a recovery time less than 50ns, or Schottky diodes with low junction capacitance.

For this application a 200V, 6A, ultra-fast recovery rectifier diode PDU620-13 from Diodes Inc. is selected as a secondary rectifier diode.

Step 9: Bias Winding Supply Configuration

The MAX17595 is implemented with a 20V V_IN UVLO wake-up level with 13V hysteresis to optimize the size of bias capacitor. A simple RC circuit is used to start up the MAX17595. To sustain the operation of the circuit, the input supply to the IC is bootstrapped through diode D2 as shown in Figure 8.

Use V_BIAS = 12V. Bias winding turns ratio k_b can be calculated as follows:

In isolated applications where a bias winding configuration is used to power up the MAX17595, C_START can be calculated as follows:

C_START = 0.75 x (C_DRV + 0.1 x I_IN x t_SS + 0.04 x t_SS x Q_G x f_SW)

C_START is the startup capacitor, C_DRV is the cumulative capacitor used at the DRV pin, I_IN is the MAX17595 quiescent current, t_SS is the soft-start time, V_OUT is the output voltage, C_OUT is the output capacitor used, and Q_G is the gate charge of the primary n-channel MOSFET. Select:

C_DRV = 1µF

I_IN = 2mA

Q_G = 23nC

t_SS = 12ms

_START = 0.75 x (1µ + 0.1 x 2m x 12m + 0.4 x 12m x 23n x 140k) C_START = 3.7µF

It is recommended to consider the derating of the startup capacitor. A typical value of 4.7µF is selected as C_START, C_START = 4.7µF.

R_START can be calculated as follows:

where C_START is in µF.

R_START is divided into three equal value resistors of value 591kΩ each. Standard 1206 resistor value of 590kΩ 250mW is selected for R_IN1, R_IN2, and R_IN3, respectively.

R_IN1 = R_IN2 = R_1N3 = 590kΩ

Step 10: Feedback Resistor Selection R_U, R_B

For all the applications that use a startup network to bias the V_IN pin during the power-up sequence, calculate the feedback potential divider using the following formulas:

A standard resistor of 750Ω is selected, R_B = 750Ω.

where V_REF is the reference set by the secondary-side controller (V_REF = 1.24V for TLV431 is used in this design).

A standard resistor of 13.7kΩ is selected, R_U = 13.7kΩ.

Step 11: Soft-Start Capacitor

The soft-start period for the devices can be programmed by selecting the value of the capacitor C_SS connected from the SS pin to SGND. Capacitor C_SS can be calculated as:

C_SS = 8.264 x t_SS

where t_SS is expressed in ms and the resultant value of C_SS is in nF.

C_SS = 8.264 x t_SS = 8.264 x 12 = 99.17nF

A standard 100nF is selected as the soft-start capacitor, C_SS = 100nF.

Step 12: Input Capacitor Selection

The MAX17595 is optimized to implement offline AC-DC applications. In such applications, the input capacitor must be selected based on either the ripple due to the rectified line voltage, or based on holdup-time requirements. Holdup time can be defined as the time period over which the power supply should regulate its output voltage from the instant the AC power fails.

For the flyback converter, the input capacitor supplies the input current when the diode rectifier is off. The voltage discharge on the input capacitor, due to the input average current, should be within the limits specified. Assuming 25% ripple present on input DC capacitor, the input capacitor can be calculated as follows:

where:

η = Target efficiency = 85%

P_LOAD = 24 ×0.5 = 12W

V_INPK = Peak voltage at minimum AC voltage = 282.84V

Step 13: Output Capacitor Selection

X7R ceramic output capacitors are preferred in industrial applications due to their stability over temperature. The output capacitor is usually sized to support a step load of a certain percentage of the rated output current so that the output voltage deviation is contained to 3% of the rated output voltage. The output capacitance can be calculated by using the below expressions:

where I_STEP is the load step, t_RESPONSE is the response time of the controller, ∆V_OUT is the allowable output voltage deviation, and f_C is the target closed-loop crossover frequency. In our application, we selected f_C = 3kHz, typical bandwidth at nominal voltage for isolated applications to minimize noise and proportionally increase the gain.

Due to the DC-bias characteristics, 4 x 10µF 50V capacitors are selected as C_OUT for this design.

Capacitor values change with temperature and applied voltage. Refer to the capacitor data sheets to select capacitors that guarantee the required output capacitance across the operating range. For design calculations, use the worst-case derated value of capacitance, based on temperature range and applied voltage. In our case the worst-case derated value of capacitors is 16µF.

For the flyback converter, the output capacitor supplies the load current when the main switch is on, and therefore the output voltage ripple is a function of load current and duty cycle. Use the following expression to estimate the output capacitor ripple:

Step 14: Loop Compensation

Optocoupler feedback is used in isolated flyback converter designs for precise control of isolated output voltage. Figure 9 shows the overall scheme of the optocoupler feedback.

Use R_FB = 470Ω (typ), for an optocoupler transistor current of 1mA. Select R1 = 49.9kΩ and R2 = 22kΩ (typical values) to use the full range of available COMP voltage. U3 is a low-voltage adjustable shunt regulator with a 1.24V reference voltage. In this design a 1.24V, 0.5% shunt regulator TLV431BFTA from Diodes Inc. is selected.

Calculate R_LED using expression below:

R_LED = 400 x CTR x (V_OUT - 2.7)

R_LED = 400 x 1 x (24 - 2.7) = 8.52kΩ

A standard 8.66kΩ resistor is selected, R_LED = 8.66kΩ.

The bandwidth of typical optocouplers limits the achievable closed-loop bandwidth of opto-isolated converters. Considering this limitation, the closed-loop crossover frequency can be chosen at the nominal input voltage by selecting f_C = 3kHz. Closed-loop compensation values are designed based on the open-loop gain at the desired crossover frequency, f_C. The open-loop at f_C is calculated using the following expressions.

Three controller configurations are suggested in Application Note 5504 based on open-loop gain and the R_LED value. For typical designs, the current transfer ratio (CTR) of the optocoupler designs can be assumed to be unity. It is known that the comparator and gate-driver delays associated with the input voltage variations affect the optocoupler CTR. Depending on the optocoupler selected, variations in CTR causes wide variations in bandwidth of the closed-loop system across the input-voltage operating range. It is recommended to select an optocoupler with less CTR variations across the operating range. Checking the condition as stated in Application Note 5504:

As 0.6646 < 0.8, therefore, as stated in Application Note 5504, configuration 1 is selected. Figure 10 shows a typical schematic of configuration 1. The R_F value can be calculated from the expression below:

A typical value of 7.5kΩ is selected as R_F, R_F = 7.5kΩ. The C_F value can be calculated from the expression below:

A standard 18nF capacitor is selected as C_F, C_F = 18nF. The C_CF1 value can be calculated from the expressions below:

A standard 330pF capacitor is selected as C_CF1 = 330pF.

Step 15: EN/UVLO and OVI Setting

The device’s EN/UVLO pin serves as an enable/disable input, as well as an accurate programmable input UVLO pin. The device does not commence startup operation unless the EN/UVLO pin voltage exceeds 1.21V. The device turns off if the EN/UVLO pin voltage falls below 1.15V. A resistor-divider from the input DC bus to ground can be used to divide down and apply a fraction of the input DC voltage (V_DC) to the EN/UVLO pin. The values of the resistor-divider can be selected so the EN/UVLO pin voltage exceeds the 1.23V turn-on threshold at the desired input DC bus voltage. The same resistor-divider can be modified with an additional resistor (R_OVI) to implement input overvoltage protection in addition to the EN/ UVLO functionality as shown in Figure 11.

When voltage at the OVI pin exceeds 1.21V the devices stop switching and resume switching operations only if voltage at the OVI pin falls below 1.15V. For given values of startup DC input voltage (V_START) and input overvoltage-protection voltage (V_OVI), the resistor values for the divider can be calculated as follows:

Select R_OVI = 24.9kΩ.

where V_OVI = maximum allowed overvoltage = 260 x 1.414 = 367.69V.

A standard 20kΩ resistor is selected, where R_EN = 20kΩ.

The same resistor-divider can be modified to implement input overvoltage protection. When the voltage at the OVI pin exceeds 1.215V (typ), the device stops switching. The device resumes switching operations only if the voltage at the OVI pin falls below 1.1V (typ).

In universal AC input applications, R_SUM may need to be implemented as equal resistors in series (R_DC1, R_DC2, and R_DC3) so that voltage across each resistor is limited to its maximum operation voltage.

A standard 2.8MΩ resistor is selected for R_DC1, R_DC2, and R_DC3.