How to use Multi-Function GPIs?

Introduction

The MAX77812 has two general-purpose inputs (GPI0 and GPI1) which can be configured as the enable function of regulators, output voltage selection, low-power mode control, and ‘no function’. The function of these two inputs is programmable through the I²C/SPI (GPI_FUNC register) on the fly.

Enable Control

When GPIx are configured as the output-enable function, the enable logic of a specific regulator is an ‘OR’ logic of GPIx and the corresponding enable register bit (Mx_EN). For example, the default function of GPI0 is Master 3 Enable (GPI0_FUNC[3:0] = 0011b), so that Master 3 Enable is controlled by GPI0 and the M3_EN bit. If GPI0 is set high earlier than ‘Global Enable (EN)’ input, Master 3 is enabled earlier than other master phases, as shown in Figure 1. The two GPIs can be configured as the same enable function (e.g., M2_EN = GPI0_FUNC[3:0] = GPI1_FUNC[3:0] = 0010b). In this case, those inputs are ORed with the M2_EN bit. The GLB_EN function (GPIx_FUNC[3:0] = 0000b) allows the host processor to enable all the masters in sequence based on the STUP_DLYx registers. Note that M1 through M4 are defined by the PH_CFG0, PH_CFG1, and PH_CFG2 inputs.

Voltage Selection

The MAX77812 BUCK has two additional output voltage control registers (Mx_VOUT_D[7:0] and Mx_VOUT_S[7:0]), besides Mx_VOUT[7:0]. Those two additional registers are for storing the default output voltage and the system sleep mode output voltage for a specific host processor.

When GPIx are configured as a voltage selection function, the output voltage of a specific regulator is set by Mx_VOUT_D[7:0] and Mx_VOUT_S[7:0] registers based on the GPIx logic level. For example, if the function of GPI0 is programmed as Global Voltage Selection (GPIx_FUNC[3:0] = 0101b), the output voltages of all the master phases are toggled by GPI0 based on the preset values in Mx_VOUT_D[7:0] (GPI0 = HIGH) and Mx_VOUT_S[7:0] (GPI0 = LOW) registers. In case the two GPIs are configured as the same voltage selection function, those inputs are ORed. During the output voltage transition, the ramp-up/down slew rate is controlled by the B_RU_SR[2:0] and B_RD_SR[2:0] registers.

Low-Power Mode

When GPIx are configured as a Low-Power Mode (LPM) enable function, the Low-Power Mode enable logic of a specific master phase is an ‘OR’ logic of GPIx and the corresponding enable register bit (Mx_LPM). For example, if GPI0_FUNC[3:0] = 1011b, the LPM enable of Master 1 is controlled by GPI0 and M1_LPM bit. In case the two GPIs are configured as the same LPM enable function (i.e., GPI0_FUNC[3:0] = GPI1_FUNC[3:0] = 1100b), those inputs are ORed with the M2_LPM bit. The GLB_LPM function (GPIx_FUNC[3:0] = 1010b) allows the host processor to enable Low-Power Mode for all the masters at the same time.