# Buck Power Stage Design Equations

### Abstract

This application note explains how the integrated buck converter power stage is constructed by selecting the appropriate external components to achieve a step-down voltage powering other modules.

### Introduction

Switching regulators are always the choice when the system has high power requirements. They provide the high efficiency and compact PCB solution size for a satisfactory power supply. This application note provides equations to guide the selection of external components needed for a step-down switching regulator when achieving a tailored voltage.

### Buck Converter Configuration

As a basic step-down switching regulator configuration shown in Figure 1, when the high-side switch is turned on at the beginning of a clock switching cycle, the low-side switch is turned off at the same time. VLX equals supply voltage VIN; when the high-side switch is turned off, the low-side switch is turned on within the rest time interval of a clock switching cycle, and VLX equals ground voltage neglecting the voltage drop across high-side and low-side PowerFETs introduced by switching currents IHS and ILS flowing through the loop, respectively. The square wave signal appearing on the VLX is passed through the LC filter, generating a constant output voltage VOUT, which is controlled by the duty cycle D of VLX.

Meanwhile, during the high-side switch ON time interval, the inductor current ILX ramps up to store the energy of inductor, and opposite to the low-side switch ON time interval, ILX ramps down to discharge the energy stored inside the inductor. The average value of the inductor current ILX maintains the DC load supplied from the switching regulator, and the inductor ripple current flows into the output capacitor, causing the output voltage ripple by capacitance and output capacitor equivalent series resistance (ESR).  ### Selecting the Inductor

When in continuous conduction mode, the power switch consumes power loss within each state in a switching cycle. The increased inductor current still equals the decreased inductor current. The duty cycle is arranged with the following equation: where the parameters are:
VOUT: Regulated output voltage
VIN: Supply input voltage
VDS1: Voltage drop across HS switch
VDS2: Voltage drop across LS switch

The duty cycle is determined simply by the input voltage and output voltage when neglecting the VDS1 and VDS2: The higher inductance value generates a smaller current ripple ΔILX and peak current value IPEAK, which determines the maximum load current the switching regulator IC output, also inducing a smaller output voltage ripple. The IPEAK should be less than the minimum value of the ILIM the IC can provide.

The switching regulator IC data sheet provides the inductor selection range, normally a fixed nominal value \pm tolerance%, and the device internal slope compensation is optimized for the external inductor value selected within the acceptable range. Once the inductor value is selected, the peak current is derived as DC output load plus half inductor ripple current.

The inductor ripple current and peak current are expressed as:  where the parameters are:
VOUT: Regulated output voltage
VIN: Supply input voltage
D: Duty cycle derived from Equation (2)
fsw: Switching frequency on system
L: Inductor value

The RMS current flowing through the inductor is: where the parameters are:
ΔILX: Inductor ripple current value from Equation (3)

Select inductors having a higher root mean square (RMS) current rating to avoid overheating impacting the efficiency and performance. The saturation current of the inductor stated in the data sheet should be larger than the maximum value of IPEAK in a given range of VIN so that the inductance value does not drop too much by a certain number. A smaller inductor value has low cost and saves PCB area, but has larger current ripple, conducting more AC core power loss dissipated on it, combining with the conduction power loss from the DCR value of the inductor. The significant power dissipated on the inductor also heats up the whole compact solution area, lowering efficiency, especially for heavy output load current.

### Selecting the Input Capacitor

When the high-side switch is in the ON state, the switching current flowing on the IC input path carries switching noise, and the input capacitor filters out most noise effectively and reduces input voltage ripple. The larger the load current drawn from the output, the larger the voltage ripple that is seen on the input. Place the input ceramic capacitor as close to the switching regulator as possible.

Calculate the input capacitance for a specified input voltage ripple as: where the parameters are:
D: Duty cycle derived from Equation (2)
fsw: Switching frequency on system
ΔVIN: Input voltage ripple requirement

The input voltage ripple contribution from the ESR is expressed as: where the parameters are:
ΔILX: Inductor ripple current value from Equation (3)
RESR: Equivalent series resistance of output capacitors network

The input capacitor RMS current is expressed as: where the parameters are:
VOUT: Regulated output voltage
VIN: Supply input voltage

The ICIN(RMS) value should be less than the RMS rating of capacitors stated in the data sheet. Use low ESR ceramic capacitors to minimize the supply voltage ripple when large current ripple is flowing through input so that the X7R dielectric material has better temperature characteristics to handle less capacitance change with temperature rise on capacitors.

The actual ceramic capacitance should be larger than the value calculated above to give some margin on the capacitance loss by DC bias voltage derating. Follow the data sheet component selection guide for minimum ceramic capacitance needed to stabilize the input voltage. One 0.1µF ceramic capacitor should be preferably placed in parallel, decoupling high frequency noise on the input. Add aluminum bulk capacitance to provide large current during load transient and maintain an allowable input voltage deviation.

### Selecting the Output Capacitor

The output voltage ripple is contributed by the capacitor elements capacitance and ESR in steady state. Use low ESR, X7R ceramic capacitors to minimize the output voltage ripple.

The output capacitance with a specific output voltage ripple requirement is expressed as: where the parameters are:
ΔILX: Inductor ripple current calculated value from Equation (3)
fsw: Switching frequency on system
ΔVOUT: Output voltage ripple requirement

The output voltage ripple contribution from ESR is expressed as: where the parameters are:
ΔILX: Inductor ripple current calculated value from Equation (3)
RESR: Equivalent series resistance of output capacitors network

The capacitance is usually determined by the fast load transient response once the output voltage ripple is no longer a problem. Capacitance satisfies the voltage overshoot during the transient response while also meeting the undershoot requirement, because the inductor discharging slew rate is slower when releasing load relative to the faster inductor charging slew rate when applying load step on output.

The output capacitance to maintain the overshoot voltage within a specified voltage change is expressed as: where the parameters are:
L: Inductor value
ΔVO: Output voltage change requirement of load transient response
VOUT: Regulated output voltage

Select the recommended output capacitance as in the data sheet per its inductor value to get an optimal phase margin.

Output voltage is set either by the fixed internal resistor divider, or adjusted by the external resistor network, if applicable, with feedback to the switching regulator IC. The current IRT flowing through the top resistor RT should be larger than 100 times of the leakage current IFB going into the feedback pin of the IC to maintain voltage accuracy on the output. Add a small feedforward capacitor CFF in parallel with the top resistor RT to produce a boost zero in the feedback control loop to optimize phase margin.

Follow the data sheet to choose the recommended bottom resistor RB in Figure 3 as a smaller value in kΩ. Then, the top resistor RT is calculated as follows: where the parameters are:
RB: Bottom resistor in adjustable resistor divider network as suggested from the data sheet
VOUT: Desired output voltage
VFB: Regulated feedback voltage ### Power Dissipation

At a particular operating condition, the output power POUT is fixed with given output voltage VOUT and load current IOUT. The less the power loss PLOSS of the system, the higher the efficiency η (η = POUT/(POUT + PLOSS)). The power loss of an inductor comprises DC conduction loss (IOUT2 × RDCR) and AC core loss, which is provided by the inductor on the specific inductor power model neglected in Equation (13). where the parameters are:
VOUT: Regulated output voltage
η: Efficiency of regulator
RDCR: Inductor DC resistance

The power consumption inside the device is transformed into heat, increasing the junction temperature. The junction temperature of the die TJ exceeds the maximum limit of the operating temperature TJMAX indicated in the data sheet, and degrades the lifetime and affects product reliability.

To estimate the junction temperature in a given ambient TA: where the parameters are:
TA: Ambient temperature
ϴJA: Thermal resistance of junction to ambient as suggested in the data sheet
PLOSS: Power loss inside device from Equation (13)

Some regulators have an embedded die temperature monitor function, enabling the junction temperature indicated in a way for voltage to be measured on an individual TEMP pin directly, no matter which ambient temperature the regulator is operating in.

The thermal management of power switching regulator solutions is challenging when applications are eager for high power supplies. Fast switching frequency allows the use of more compact components to save space for integrating more solutions of features, and introducing more heat transfer between each other. An optimized PCB layout and thermal efficient IC package cools the junction temperature to make it more suitable for higher ambient operating conditions. Choosing a multiphase configuration spreading power averagely onto multiple parallel power trains relieves thermal pressure, instead of it becoming a hot spot on the PCB, burning neighbor components.