Tick-Tock, Tick-Tock


My clock is accurate to 1 ppm—what could possibly need improvement?

RAQ:  Issue 6


The phase noise or jitter. The performance of any ac sampling system is critically dependent on the use of a sampling clock with adequately low jitter.

A quarter of a century ago I was technical advisor to a Parliamentary Committee on CB Radio. We met at Westminster Hall in the Houses of Parliament in London, almost directly under Big Ben, whose chimes punctuated our deliberations. I frequently used Big Ben as an example when explaining the importance of various features of clocks and oscillators.

In a sampled data system, a changing signal is sampled at regular intervals and the signal is processed by performing calculations on the samples. If an oscillator has jitter, the clock edges occur earlier or later than they would in a jitter-free clock. The frequency accuracy is unaffected, only the exact timing of individual transitions varies.

If an edge comes early, the signal being sampled will not yet have reached its correct value, and if it comes late, the signal will have moved on – so to achieve accuracy in a sampled system it is important to have adequately low jitter on the system clock. In fact, frequency accuracy is often far less important. Obviously, the faster the sampled signal is changing, the greater the error will be for a given amount of jitter. The clock frequency is irrelevant – it is the frequency of the analog signal being sampled (in the case of the ADC) or signal being synthesized (in the case of the DAC) that matters.

Although the problem can be significant at quite modest signal frequencies (I have memories of digital audio systems with performance devastated by inappropriate clock oscillators – one a 555 timer, another an interrupt-driven microprocessor) it becomes critical in modern digital radios using IF sampling at signal frequencies of tens or hundreds of MHz. To give numbers, a perfect ADC (no imperfections of any sort) working with a 100 MHz signal and a clock with one pico second (1E-12 seconds) rms jitter cannot achieve a resolution greater than 10 bits.

Links to information on the relevant formula, low noise clock circuits, and circuit techniques that ensure a low clock jitter signal is not degraded before it reaches the circuits it drives, are on the website below. A simple illustration of the difference between clock accuracy and clock jitter is to consider what would happen if Big Ben’s hands always pointed to the exact time, but the chime occurred randomly up to five minutes early or late.

The Effect of Clock Noise on Sampled Data Systems (ppt)



James Bryant

James Bryant自1982年起担任ADI公司的欧洲应用经理,直至2009年退休为止。至今仍从事撰写和咨询工作。他拥有英国利兹大学的物理学和哲学学位,同时还是注册工程师(C.Eng.)、欧洲注册工程师(EurEng.)、电机工程师协会会员(MIET)以及对外广播新闻处(FBIS)会员。除了热情钻研工程学外,他还是一名无线电爱好者,他的呼叫代号是G4CLF。