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AD800:  45或52 Mbps时钟和数据恢复IC

产品详情

AD800和AD802采用二阶锁相环结构,对不归零(NRZ)数据执行时钟恢复和数据重定时。这种结构可支持20 Mbps至160 Mbps范围内的数据速率。此处所述的产品规定以标准电信比特率工作。AD800-45和AD800-52分别支持45 Mbps DS-3和52 Mbps STS-1。AD802-155支持155 Mbps STS-3或STM-1。                                    

与其它基于PLL的时钟恢复电路不同,这些器件不需要前同步码或外部VCXO来锁定输入数据。电路利用两个控制环路采集频率和相位锁定。首先由频率采集控制环路采集输入数据的时钟频率,然后由锁相环采集输入数据的相位,并确保输出信号相位跟踪输出数据相位的变化。电路的环路阻尼取决于用户所选电容的值;它决定抖动峰值和性能,并影响采集时间。这些器件的抖动峰值为0.08 dB;当阻尼系数为5时,可以在4 X 105 位周期内锁定随机或加扰数据。

在采集过程中,鉴频器提供一个频率采集(FRAC)信号,指示器件尚未锁定输入数据。此信号是一系列脉冲,出现在输入数据与同步时钟信号之间的周跳点。一旦电路采集到频率锁定,FRAC输出就不会出现脉冲。

器件中内置经过精密调整的VCO,不需要用于设置中心频率的外部器件,从而也不需要对这些器件进行调整。无输入数据时,VCO提供器件中心频率±20%范围内的时钟输出。

取得专利的鉴相器具有出色的性能,因而AD800和AD802几乎没有码抖动。总环路抖动为20°峰峰值。抖动带宽由掩模可编程小数环路带宽决定。AD800用于90 Mbps以下的数据速率,标称环路带宽为中心频率的0.1%。AD802用于90 Mbps以上的数据速率,环路带宽为中心频率的0.08%。

所有器件均采用+5 V或-5.2 V单电源供电。

特点和优势

  • 标准产品
    44.736 Mbps—DS-3
    51.84 Mbps—STS-1
    155.52 Mbps—STS-3 或STM-1
  • 接受NRZ数据,无需前同步码
  • 恢复时钟和重定时数据输出
  • 锁相环型时钟恢复,无需晶振
  • 随机抖动:20°峰峰值
  • 码抖动:几乎消除
  • 兼容10KH ECL
  • 单电源供电:–5.2 V或+5 V
  • 宽工作温度范围:–40°C至+85°C

AD800功能框图

AD800 Diagram
AD800功能框图

文档

快讯名称 内容类型 文件类型
AD800/AD802: Clock Recovery and Data Retiming Phase-Locked Loop Data Sheet (Rev B, 12/1993) (pdf, 253 kB) 产品数据手册 PDF
AN-851: 一种WiMax双下变频IF采样接收机设计方案[中文版]  (pdf, 421 kB) 应用笔记 PDF
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design  (pdf, 262 kB) 应用笔记 PDF
Clock and Timing ICs  (pdf, 4970 kB) 概况 PDF
RAQs index 非常见问题解答 HTML
Why do I see reference spurs? 常见问题解答 HTML
Why is my phase noise shape changing when I change the PLL settings? 常见问题解答 HTML
Why doesn't the PLL make my reference input and the clock outputs line up? 常见问题解答 HTML
How do I optimize my PLL loop for the best phase noise and/or jitter? 常见问题解答 HTML
My loop is not locking. How do I debug this? 常见问题解答 HTML
How long does it take for the PLL to lock? 常见问题解答 HTML
Help! My PLL came unlocked over temperature. 常见问题解答 HTML
How do I choose between active and passive filter in PLL loop? 常见问题解答 HTML
Should I reference the passive filter to ground? or supply? 常见问题解答 HTML
How do the PLLs in the AD951x parts compare to other ADI PLLs? 常见问题解答 HTML
How does the clock clean-up function of the AD951x parts work? 常见问题解答 HTML
Why do I want to run a fast PFD frequency? 常见问题解答 HTML
Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins? 常见问题解答 HTML
Why can't I use a bandpass filter for my loop filter? 常见问题解答 HTML
Should I tie my loop filter to ground or PLL supply? 常见问题解答 HTML
The loop filter was working great until I changed the divide ratio in PLL. What happened? 常见问题解答 HTML
How do I use a VCO with a supply greater than 5V? 常见问题解答 HTML
What suppliers do you recommend for VCO/VCXOs? 常见问题解答 HTML
Do VCXOs have better phase noise and jitter performance than VCOs? 常见问题解答 HTML
How do I know which VCO will work best with the AD9510? 常见问题解答 HTML
Is there an advantage to running a higher VCO frequency than the output frequency? 常见问题解答 HTML
How do I determine if a VCO is good enough for my purpose? 常见问题解答 HTML
Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip? 常见问题解答 HTML
Do different divide ratios cause variations in jitter? 常见问题解答 HTML
I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips? 常见问题解答 HTML
Do divide ratios change the propagation delay? 常见问题解答 HTML
I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset? 常见问题解答 HTML
On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter? 常见问题解答 HTML
Why doesn't the mini-divider support the divide ratio I want? 常见问题解答 HTML
I want to use the variable delay adjust, but the jitter is too high. What can I do? 常见问题解答 HTML
I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on? 常见问题解答 HTML
What is the difference between the coarse phase adjust and the fine delay adjust? 常见问题解答 HTML
What is the fine delay adjust which is available on certain LVDS/CMOS outputs? 常见问题解答 HTML
Does the fine delay adjust affect the jitter? 常见问题解答 HTML
Why is the fine delay adjust not available on all the outputs? 常见问题解答 HTML
Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11? 常见问题解答 HTML
Will the AD9510 work without a reference input signal? 常见问题解答 HTML
What are the best clock sources for a distribution-only design? 常见问题解答 HTML
I am not using the CLK1 input on the AD9510. Can I just leave it floating? 常见问题解答 HTML
How good does my input signal need to be? 常见问题解答 HTML
I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked. 常见问题解答 HTML
Can I shift the threshold on clocks for single-ended inputs? 常见问题解答 HTML
The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510? 常见问题解答 HTML
Will differential or single-ended inputs/outputs improve my jitter? 常见问题解答 HTML
Why should I use differential rather than single-ended? 常见问题解答 HTML
How do I feed a single-ended signal into a differential input? 常见问题解答 HTML
Why do you recommend AC coupling, rather than DC coupling, at the clock inputs? 常见问题解答 HTML
Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts? 常见问题解答 HTML
Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs? 常见问题解答 HTML
On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate? 常见问题解答 HTML
I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong? 常见问题解答 HTML
Can I use the 951X clocks to drive a mixer (RF LO)? 常见问题解答 HTML
My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications? 常见问题解答 HTML
I have an input present at the clock input, but I'm not seeing an output? 常见问题解答 HTML
What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away? 常见问题解答 HTML
What clock frequency comes out of the AD9510 outputs when you first apply power to the device? 常见问题解答 HTML
Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF) 常见问题解答 HTML
I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz? 常见问题解答 HTML
What should I do with unused channels on the AD9510? 常见问题解答 HTML
Can I tri-state the AD9510 outputs? 常见问题解答 HTML
On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window? 常见问题解答 HTML
What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter? 常见问题解答 HTML
Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output? 常见问题解答 HTML
What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs? 常见问题解答 HTML
Does the AD9510 support 2.5V PECL? 常见问题解答 HTML
How much bandwidth is required to process a PECL or LVDS output? 常见问题解答 HTML
If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output? 常见问题解答 HTML
If I change the level of PECL output, does it affect the jitter? 常见问题解答 HTML
What is the best way to terminate LVPECL outputs to get lowest jitter? 常见问题解答 HTML
Is it okay to AC-couple PECL or LVDS outputs? 常见问题解答 HTML
What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs? 常见问题解答 HTML
What is the proper termination (value and location) for outputs? 常见问题解答 HTML
Are outputs short-circuit protected? 常见问题解答 HTML
Are the CMOS drivers on the clock devices complementary? 常见问题解答 HTML
Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)? 常见问题解答 HTML
I have pulled SYNCB low, but I still have output from a channel. Why? 常见问题解答 HTML
Why can I not get the same output amplitude or rise and fall times as stated in your datasheet? 常见问题解答 HTML
The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work? 常见问题解答 HTML
May I use the AD9540 for spread spectrum clocking? 常见问题解答 HTML
Can I get two clock outputs from the AD9540? 常见问题解答 HTML
What's the advantage of a DDS-based clock generator? 常见问题解答 HTML
Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter? 常见问题解答 HTML
I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications? 常见问题解答 HTML
On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong? 常见问题解答 HTML
How do you determine the bandwidth over which phase noise is integrated to obtain jitter? 常见问题解答 HTML
Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification? 常见问题解答 HTML
How do harmonic spurs in the output spectrum affect jitter (random or deterministic)? 常见问题解答 HTML
When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed? 常见问题解答 HTML
How do you specify jitter? 常见问题解答 HTML
How do I use the clock part for jitter clean-up? 常见问题解答 HTML
If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers? 常见问题解答 HTML
Does jitter vary with different clock frequencies? How about phase noise? 常见问题解答 HTML
I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts? 常见问题解答 HTML
Do you guarantee performance shown in ADIsimCLK? 常见问题解答 HTML
Who do I contact for technical support on ADIsimCLK? 常见问题解答 HTML
Should I use the minimum charge pump current settings in order to minimize power? 常见问题解答 HTML
Can I run CMOS outputs at 5V? 常见问题解答 HTML
Can I use different power supply voltages for the PECL output drivers? 常见问题解答 HTML
Is .01 uF sufficient for power supply pin bypass? 常见问题解答 HTML
My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power? 常见问题解答 HTML
Why don't you spec psrr and cmrr in the datasheet? 常见问题解答 HTML
How do I get two AD951x (with PLL) to synchronize to the same reference input edge? 常见问题解答 HTML
I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN? 常见问题解答 HTML
How do I synchronize multiple clock devices? 常见问题解答 HTML
What happens if I run the part in an ambient environment which exceeds 85°C? 常见问题解答 HTML
How can I determine the die temperature of your device? 常见问题解答 HTML
My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND? 常见问题解答 HTML
What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package? 常见问题解答 HTML
术语表 专业词汇表 HTML

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Sample样片申请及购买

价格,封装及供货状态

AD800 型号选项
产品型号 封装 引脚 温度范围 包装和数量 报价*(100-499) 报价*1000 pcs RoHS 查看PCN/PDN 查看库存/
购买/样片
AD800-52BR 产品状态: 最后订购时间 20 ld SOIC - Wide 20 工业 Tube, 37 $ 24.79 $ 22.09 N  材料信息 查看PCN/PDN 订购
AD800-52BRRL 产品状态: 最后订购时间 20 ld SOIC - Wide 20 工业 Reel, 1000 - - N  材料信息 查看PCN/PDN 订购
AD800-52BRZ 产品状态: 量产 20 ld SOIC - Wide 20 工业 Tube, 37 $ 21.21 $ 18.90 Y  材料信息 查看PCN 订购
AD800-52BRZRL 产品状态: 量产 20 ld SOIC - Wide 20 工业 Reel, 1000 - - Y  材料信息 查看PCN 订购
帮助

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