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Download this article in PDF format. (228 KB) Front-End Amplifier and RC Filter Design for a Precision SAR Analog-to-Digital Converter Successive-approximation (SAR) ADCs offer high resolution, excellent accuracy, and low power consumption. Once a particular precision SAR ADC has been chosen, system designers must determine the support circuitry needed to obtain the best results. The three principal areas to consider are the The front end consists of two parts: the driving amplifier and the RC filter. The amplifier conditions the input signal—as well as acting as a low-impedance buffer between the signal source and the ADC input. The RC filter limits the amount of out-of-band noise arriving at the ADC input and helps to attenuate the kick from the switched capacitors in the ADC’s input. Choosing the right amplifier and RC filter for a SAR ADC can be a challenge, especially when the application needs to differ from the routine data sheet usage of the ADC. Looking at the various application factors that influence amplifier and RC choice, we provide design guidelines that lead to the best solution. Major considerations include
Figure 1 shows a typical amplifier, single-pole RC filter, and ADC. The ADC input presents a switched-cap load to the driving circuitry. Its 10-MHz input bandwidth means that low-noise is needed over a wide bandwidth to get a good signal-to-noise ratio (SNR). The RC network limits the bandwidth of the input signal and reduces the amount of noise fed to the ADC by the amplifier and upstream circuitry. Too much band limiting will increase the settling time and distort the input signal, however.
The minimum RC value needed to settle the ADC input while also optimally band limiting the noise can be calculated assuming exponential settling of a step input. To calculate the size of the step, we need to know the input signal frequency, amplitude, and ADC conversion time. The reverse settling time.
The maximum undistorted rate of change of a sine wave signal with a given input frequency can be calculated as
If the conversion rate of the ADC is considerably higher than the maximum input frequency, the maximum amount the input voltage has changed during the conversion time is given by
This is the maximum voltage step that is seen by the capacitive DAC when it is switched back to acquire mode. This step is then attenuated by the parallel combination of the DAC’s capacitance and that of the external capacitor. For this reason, it is important that the external capacitor be relatively large—a few nanofarads. This analysis will assume that the on resistance of the input switch has a negligible effect. The step size that now needs to be settled is given by
Next, calculate the time constant to settle the ADC input to ½ LSB during the acquisition time of the ADC. Assuming exponential settling of the step input, the required RC time constant, τ, is
where N is the number of time constants required to settle. The number of time constants required can be calculated from the natural logarithm of the ratio of the step size, _{TC}V to the settling error—which in this case is ½ LSB,_{STEP},
giving
Substituting this in the previous equation gives
And the equivalent RC bandwidth is
This step is then attenuated by the charge from the external capacitor. Using a DAC capacitance of 27 pF and assuming a 2.7-nF external capacitance, the attenuation factor will be about 101. Plugging these numbers into the equation for
Next, calculate the number of time constants to settle to ½ LSB at 16 bits; with a 5-V reference
The acquisition time is
Calculating for τ,
So, bandwidth = 3.11 MHz and R
This relationship between the minimum bandwidth, throughput, and input frequency shows that higher input frequencies require a higher RC bandwidth. Similarly, higher throughput, which results in lower acquisition time, increases the RC bandwidth. The acquisition time has the largest influence on the bandwidth needed; if it were doubled (reducing throughput), the bandwidth required would be halved. This simplified analysis does not include second-order charge kickback effects that become dominant at lower frequencies. In the case of very low input frequencies (<10 kHz), including dc, there will always be ~100 mV of voltage step to settle on the cap DAC. This number should be used as the minimum possible voltage step in the analysis above. A
When using a multiplexed input in the above example, the required filter bandwidth for linear response would increase to
This can be checked for the calculated RC bandwidth by using Table 1. From the table, 11 time constants are needed to settle a full-scale step to 16 bits (Table 1). For the calculated RC, the forward settling time of the filter is 11 × 40.49 ns = 445 ns, which is much less than the conversion time of 710 ns. The forward settling does not necessarily have to occur completely during the conversion time (before the cap DAC gets switched to the input), but the combined forward and reverse settling time should not exceed the required throughput rate. Forward settling is less important for low-frequency inputs, as the rate of change of the signal is much lower.
With an approximate filter bandwidth calculated, the individual values of R It is important that the value of R
Larger series resistance values can be tolerated for low input frequencies (<10 kHz). The distortion is also a function of the input signal amplitude; a lower amplitude will allow a higher value of resistance for the same distortion level. Calculating for R The nominal RC values calculated here are useful guidelines, not a final solution. Choosing the right balance between the R
- Amplifier large and small signal bandwidth
- Settling time
- Amplifier noise specification and effect on system noise
- Distortion
- Headroom requirements for distortion and resulting supply rails
An amplifier’s Another way of looking at the forward settling requirement is to look at the amplifier’s settling-time specification, usually the time required to settle to a percentage of the specified step size. For 16- to 18-bit performances, settling to 0.001% is typically required—but most amplifiers are specified for 0.1% or 0.01%, with varying step sizes; hence, some compromises with the numbers are needed in order to get a good idea whether the settling behavior could be acceptable for the ADC throughput. The ADA4841-1 specified settling time to 0.01% is 1 μs for an 8-V step. In a muxed application driving the AD7980 at 1 MSPS (1-μs period), it will not be able to settle the input in time for a full-scale step, but a lower throughput of, say, 500 kSPS may be possible. The RC bandwidth is important in determining the maximum amount of noise allowed in the amplifier. Amplifier noise is generally specified by low-frequency 1/f noise (0.1 Hz to 10 Hz) and wideband noise spectral density at a higher frequency on the flat part of the noise curve (Figure 7).
The total noise referred to the input of the ADC can be calculated as follows. First, calculate the noise due to the wideband spectral density of the amplifier over the RC bandwidth
where N = amplifier circuit noise gain, and BW = RC bandwidth in Hz._{RC}Next, add in the low-frequency 1/f noise, which is usually specified peak-to-peak and needs to be converted to rms, typically using this equation
where = 1/f peak-to-peak noise voltage and Total noise is then given by the root-sum-square:
This total noise should be ~1⁄10 of the noise of the ADC in order to have a minimal effect on the overall SNR. Higher noise may be allowable, depending on the target system’s SNR. For example, if the ADC’s SNR = 91 dB, with
From this number, it is easy to work out maximum allowable specifications for 1/f noise and wideband noise spectral density. Assuming that the amplifier under consideration has negligible 1/f noise, operates at unity gain, and uses a filter with the RC bandwidth calculated previously, 3.11 MHz, then
Thus, the amplifier must have a wideband noise spectral density ≤ 2.26 nV/√ Hz. The ADA4841-1 meets this criterion with a specification of 2.1 nV/√ Hz. Another important specification to consider for the amplifier is the distortion at a particular input frequency. Typically, for best performance, total harmonic distortion (THD) of ~100 dB is required at 16 bits and ~110 dB for 18-bit ADCs at the input frequency of interest. Figure 8 shows a typical distortion vs. frequency plot for the ADA4841-1 for a 2-V p-p input signal.
Instead of showing total harmonic distortion, the plot is broken out into the generally most dominant second and third harmonic components. The ADA4841-1 is sufficiently clean to drive an 18-bit ADC up to ~30 kHz with excellent distortion characteristics. As the input frequency approaches 100 kHz and beyond, the distortion performance begins to degrade. For lower distortion at higher frequencies, a higher-power, wider-bandwidth amplifier will be required. Larger signals will also reduce performance. For an ADC input of 0 V to 5 V, the distortion performance signal range increases to 5-V p-p. This will produce differing performance from the distortion plot shown in Figure 8, so the amplifier potentially requires testing to make sure it still meets requirements. Figure 9 compares distortion performance at several output voltage levels.
The THD can also be affected by the headroom—the difference between the amplifier’s maximum practical input/output swing and the positive and negative supply rails. Amplifiers can have rail-to-rail inputs and/or outputs, or require up to 1 V or more headroom. Even with rail-to-rail inputs/outputs, it is difficult to get good distortion if running at a signal level that is close to the rails of the amplifier. For this reason, it is a good idea to choose supply levels that keep the maximum input/output signal away from the rails. Consider, for example, an ADC with a 0 V-to-5-V input range driven by an ADA4841-1 amplifier and a need to maximize the range of the ADC. The amplifier has a rail-to-rail output and a 1-V headroom requirement on the input. If used as a unity gain buffer, at least 1-V input headroom is needed, so the positive supply must be at least 6 V. The output is rail to rail but still can only drive to within ~25 mV of ground or the positive rail, so a negative rail is needed in order to drive all the way to ground. The negative rail could be –1 V, for example, in order to leave a margin for distortion performance. The negative supply could be eliminated if it were feasible to lose some SNR by accepting a reduction in the ADC input range. For example, if the ADC’s input range were to be reduced to 0.5 V to 5 V, this 10% loss of the ADC range would result in a Thus, when selecting the amplifier, it is important to consider the input and output signal range requirements, as this will determine the supply voltage needed. In this example, an amplifier rated for 5-V operation would not suffice; the ADA4841-1 is specified up to 12 V, however, so using a higher supply voltage will allow it to work well—with adequate supply margins.
^{®} ADCs—and for use in portable instrumentation, industrial process control, and medical equipment. Unity-gain stable, its specifications include 60-μV input offset voltage, 114-dB open-loop gain, 114-dB common-mode rejection, 80 MHz bandwidth (–3 dB), 12-V/µs slew rate, and 175-ns settling time to 0.1%. The input signal can extend normal mode and 40 μA in power-down mode. Available in an 8-lead SOIC package, it is specified from –40ºC to +125ºC and priced at $1.59 in 1000s.
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range, it specifies 91.5-dB signal-to-noise-and-distortion (SINAD), –110-dB total harmonic distortion (THD), and ±1.25-LSB maximum integral nonlinearity. Its successive-approximation architecture ensures that there will be no pipeline delays; and daisy-chaining allows several ADCs to share a single bus. Automatically powering down between conversions, its power consumption scales with throughput rate. Operating on a single 2.5-V supply, the AD7980 consumes 7 mW at 1 MSPS, 70 μW at 10 kSPS, and 350 pA in standby mode. Available in a 10-lead MSOP package, it is specified from –40ºC to +85ºC and priced from $11.95 in 1000s.I invite you to comment on adc front ends in the Analog Dialogue Community on EngineerZone.
Understanding PulSAR ADC Support Circuitry.AN-1024 Application Note. MT-048 Tutorial. Ardizzoni, John, Ardizzoni, John. Ardizzoni, John, and Jonathan Pearson. Data Conversion Knowledge Resource. http://www.analog.com/en/data-conversion-knowledge-resource/conversions/index.html.
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