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DDS Devices Generate High-Quality Waveforms Simply, Efficiently, and Flexibly
The Task of Frequency Synthesis
fOUT = εx× fC
where the scaling factor, εx, is sometimes called the normalized frequency.
The equation is always implemented using algorithms for step-by-step approximations of real numbers. When the scaling factor is a rational number, a ratio of two relatively prime integers, the output frequency and the reference frequency will be harmonically related. In most cases, however, εx can belong to a much broader set of real numbers, and the approximation process is truncated as soon as it falls within an acceptable limit.
Direct Digital Frequency Synthesis
Simply stated, a direct digital frequency synthesizer translates a train of clock pulses into an analog waveform, typically a sine, triangular, or square wave. As Figure 1 shows, its essential parts are: a phase accumulator, which produces a number corresponding to a phase angle of the output waveform, a phase-to-digital converter, which generates the instantaneous digital fraction of the output amplitude occurring at a particular phase angle, and a digital-to-analog converter (DAC), which converts that digital value to a sampled analog data point.
Figure 1. Functional block diagram of a DDS system.
For sine-wave outputs, the phase-to-digital converter is usually a sine lookup table (Figure 2). The phase accumulator counts by N, to generate a frequency related to fC according to the equation,
Figure 2. Typical DDS architecture and signal path with DAC.
Since changes to N result in immediate changes in the output phase and frequency, the system is inherently phase-continuous, a critical attribute in many applications. No loop settling time is required, in contrast to analog-type systems, such as phase-locked loops (PLLs).
The DAC is usually a high-performance circuit specifically designed to work with the DDS core (phase accumulator and phase-to-amplitude converter). In most cases, the resulting device, often a single chip, is commonly referred to as a complete DDS or C-DDS.
Practical DDS devices often integrate multiple registers to allow various frequency- and phase-modulation schemes to be realized. When included, the phase register’s contents are added after the phase accumulator. This enables the output sine wave to be phase-delayed in correspondence with a phase tuning word. This is extremely useful for phase-modulation applications in communication systems. The resolution of the adder circuit determines the number of bits in the phase tuning word and, therefore, the resolution of the delay.
Integrating a DDS engine and a DAC in a single device has advantages and disadvantages, but whether integrated or not, a DAC is required to create a high quality analog signal of exceptional purity. The DAC converts the digital sine output into an analog sine wave and may be either single-ended or differential. A few of the key requirements are low phase noise, excellent wideband (WB-) and narrow-band (NB-) spurious-free dynamic range (SFDR), and low power consumption. If it is an external component, the DAC needs to be fast enough to process the signal—so devices with a parallel port are common.
DDS vs. Other Solutions
Table 1. DDS vs. Competing Technologies—High Level Comparison
A phase-locked loop is a feedback loop comprising: a phase comparator, a divider, and a voltage-controlled oscillator (VCO). The phase comparator compares a reference frequency with the output frequency (usually divided down by a factor, N), The error voltage generated by the phase comparator is applied to the VCO, which generates the output frequency. When the loop has settled, the output will bear an accurate relationship to the reference in frequency and/or phase. PLLs have long been recognized as superior devices for low phase noise and high spurious-free dynamic range (SFDR) applications requiring high fidelity and stable signals in a specific band of interest.
Their inability to accurately and quickly tune the frequency output and waveform and their slow response limits their suitability for applications such as agile frequency hopping and some frequency- and phase-shift keying applications.
Other approaches, including field-programmable gate arrays (FPGAs) with embedded DDS engines—in combination with off-the-shelf DACs to synthesize output sine waves—solve the frequency-hopping difficulties of PLLs, but have their own weaknesses. The main system disadvantages include higher operating and interface power requirements, higher cost, large size, and additional software-, hardware-, and memory overhead for the system developer. For example, up to 72 kB of memory are required to generate a 10-MHz output signal with 60‑dB dynamic range using the DDS engine option on modern FPGAs. In addition, the designer needs to be comfortable and familiar with subtle trade-offs and the architecture of the DDS core.
As a practical matter (see Table 2), rapid advances in CMOS processing, together with modern digital design techniques and improved DAC topologies, have resulted in the DDS technology achieving power consumption, spectral performance, and cost levels that were previously unattainable for a wide range of applications. While complete DDS products will never match the highest performance and design flexibility achievable with custom combinations of high-end DAC technology and FPGAs, the size-, power- and cost benefits, coupled with the simplicity of DDS devices, may make them easily the first choice for many applications.
Table 2. Benchmark Analysis Summary—Frequency-Generation Technologies (<50 MHz)
Also note that since a DDS device fundamentally embodies a digital method of generating an output waveform, it can simplify the architecture of some solutions or make it possible to digitally program the waveform. While a sine wave is normally used to explain the function and operation of a DDS, it is easily possible to generate triangular or square (clock) wave outputs from modern DDS ICs, avoiding the need for a lookup table in the former case, and for a DAC in the latter case, where the integration of a simple yet precise comparator will suffice.
DDS Performance and Limitations
The Nyquist Criterion dictates that a minimum of two samples per cycle are required to reconstruct a desired output waveform. Image responses are created in the sampled output spectrum at K fCLOCK × fOUT. In this example, where fCLOCK = 25 MHz and fOUT = 5 MHz, the first and second images occur (see Figure 3) at fCLOCK × fOUT, or 20 MHz and 30 MHz. The third and fourth images appear at 45 MHz and 55 MHz. Note that the sin(x)/x nulls appear at multiples of the sampling frequency. In the case where fOUT is greater than the Nyquist bandwidth (1/2 fCLOCK), the first image response will appear within the Nyquist bandwidth as an aliased image (a 15-MHz signal will alias down to 10 MHz, for example). The aliased image cannot be filtered from the output with a traditional Nyquist antialiasing filter.
Figure 3. Sin(x)/x roll-off in a DDS.
In typical DDS applications, a low-pass filter is utilized to suppress the effects of the image responses in the output spectrum. To keep the cutoff requirements of the low-pass filter reasonable and the filter design simple, an accepted guideline is to limit the fOUT bandwidth to approximately 40% of the fCLOCK frequency using an economical low-pass output filter.
The amplitude of any given image in response to the fundamental can be calculated using the sin(x)/x formula. Because the function rolls off with frequency, the amplitude of the fundamental output will decrease inversely with its tuned frequency; in a DDS system, the decrease will be –3.92 dB over the dc to Nyquist bandwidth.
The amplitude of the first image is substantial—within 3 dB of the fundamental. To simplify filtering requirements for DDS applications, it is important to generate a frequency plan and analyze the spectral considerations of the image and the sin(x)/x amplitude responses at the desired fOUT and fCLOCK frequencies. Online interactive design tools supporting the Analog Devices DDS product family allow for quick and easy simulation of where images lie and allow the user to choose frequencies where images are outside the band of interest. See the Further Information and Useful Links section for additional useful information.
Other anomalies in the output spectrum, such as integral and differential linearity errors of the DAC, glitch energy associated with the DAC, and clock feedthrough noise, will not follow the sin(x)/x roll-off response. These anomalies will appear as harmonics and spurious energy in many places in the output spectrum—but will generally be much lower in amplitude than the image responses. The general noise floor of a DDS device is determined by the cumulative combination of substrate noise, thermal noise effects, ground coupling, and other sources of signal coupling. The noise floor, performance spurs, and jitter of a DDS device are greatly influenced by circuit board layout, the quality of the power supplies, and—most importantly—the quality of the input reference clock.
So choosing a stable reference clock oscillator with low jitter and sharp edges is critical. Higher frequency reference clocks allow greater oversampling, and jitter can be somewhat ameliorated by frequency division, since dividing the frequency of the signal yields the same amount of jitter across a longer period, and so reduces the percentage of jitter on the signal.
Noise—Including Phase Noise
In both cases, an increasing trend towards higher spectral purity (lower phase noise and higher spurious-free dynamic range) is coupled with low operating power and size requirements for remote or battery-operated equipment.
DDS in Modulation/Data Encoding and Synchronization
Binary frequency shift keying (BFSK, or simply FSK) is one of the simplest forms of data encoding. The data is transmitted by shifting the frequency of a continuous carrier between one (binary 1, or mark) and the other (binary 0, or space) of two discrete frequencies. Figure 4 shows the relationship between the data and the transmitted signal.
Figure 4. Binary FSK modulation.
Binary 1s and 0s are represented as two different frequencies, f0 and f1, respectively. This encoding scheme is easily implemented with a DDS device. The DDS frequency tuning word representing the output frequencies is changed so that f0 and f1 are generated from 1s and 0s to be transmitted. In at least two members of Analog Devices complete DDS product families (the AD9834 and the AD9838—see also the Appendix), the user can simply program the two current FSK frequency tuning words into the IC’s embedded frequency registers. To shift output frequency, a dedicated pin, FSELECT, selects the register containing the appropriate tuning word (see Figure 5).
Figure 5. FSK encoding using the tuning-word selector of an AD9834 or AD9838 DDS.
Phase-shift keying (PSK) is another simple form of data encoding. In PSK, the frequency of the carrier remains constant, and the phase of the transmitted signal is varied to convey the information. Several schemes can be used to accomplish PSK. The simplest method, commonly known as binary PSK (or BPSK), uses only two signal phases: 0° (Logic 1) and 180° (Logic 0). The state of each bit is determined according to the state of the preceding bit. If the phase of the wave does not change, the signal state stays the same (low or high). If the phase of the wave changes by 180°, that is, if the phase reverses—the signal state changes (low to high, or high to low). PSK encoding is easily implemented with a DDS product as most of the devices have a separate input register (a phase register) that can be loaded with a phase value. This value is directly added to the phase of the carrier without changing its frequency. Changing the contents of this register modulates the phase of the carrier, generating a PSK output. For applications that require high-speed modulation, the AD9834 and AD9838, which have pairs of phase registers, allow signals on a PSELECT pin to alternate between the preloaded phase registers to modulate the carrier as required.
More complex forms of PSK employ four or eight wave phases. This allows binary data to be transmitted at a faster rate per phase change than is possible with BPSK modulation. In four-phase modulation (quadrature PSK), the possible phase angles are 0°, +90°, −90°, and +180°; each phase shift can represent two signal elements. The AD9830, AD9831, AD9832, and AD9835 provide four phase registers to allow complex phase modulation schemes to be implemented by continuously updating different phase offsets to the registers.
I/Q Capability Using Multiple DDS Components in Synchronous Mode
A reset must be initiated after power-up and before transferring any data to the DDS. This establishes the DDS output in a known phase, which becomes the common reference angle that allows synchronization of multiple DDS devices. When new data is sent simultaneously to multiple DDS devices, a coherent phase relationship can be maintained—or the relative phase offset between multiple DDS devices can be predictably shifted by means of the phase offset register. The AD983x series of DDS products have 12 bits of phase resolution, providing an effective resolution of 0.1°.
Figure 6. Synchronizing two DDS components.
For more information about synchronizing multiple DDS devices, see AN-605 Application Note, Synchronizing Multiple AD9852 DDS-Based Synthesizers.
The information gathered on the response signal is used to determine key system information. The range of networks being tested (see Figure 7) can be quite wide, including cable integrity testing, biomedical sensing, and flow-rate measurement systems. Wherever the basic requirement is to generate frequency-based signals and compare phase and amplitude of the response signal(s) to the original signal, or if a range of frequencies needs to be excited through the system, or if test signals with different phase relationships (as in systems with I/Q capability) are required, direct digital synthesis ICs can be highly useful for digitally controlling stimulus frequency and phase through software with simplicity and elegance.
Figure 7. Typical network analysis architecture using frequency stimulus.
Cable Integrity/Loss Measurement
Figure 8. Ultrasonic flow meter.
FURTHER INFORMATION AND USEFUL LINKS
Figure 9. AD9838 evaluation software interface.
Other useful DDS information can be found on the DDS website.
Murphy, Eva and Colm Slattery. “All About Direct Digital Synthesis.” Ask The Applications Engineer—33. Analog Dialogue. Volume 38, No. 3, (2004): 8–12.
Figure 10. Block diagram of the AD9838 DDS.
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