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Download this article in PDF format. (1.5 MB) DDS Devices Generate High-Quality Waveforms Simply, Efficiently, and Flexibly
f. The general relationship can be written simply as_{OUT}
× _{x}f_{C}where the scaling factor, ε normalized frequency.The equation is always implemented using algorithms for step-by-step approximations of real numbers. When the scaling factor is a rational number, a ratio of two relatively prime integers, the output frequency and the reference frequency will be harmonically related. In most cases, however, ε
Simply stated, a direct digital frequency synthesizer translates a train of clock pulses into an analog waveform, typically a sine, triangular, or square wave. As Figure 1 shows, its essential parts are: a
For sine-wave outputs, the phase-to-digital converter is usually a sine lookup table (Figure 2). The phase accumulator counts by
where:
Since changes to The DAC is usually a high-performance circuit specifically designed to work with the DDS core (phase accumulator and phase-to-amplitude converter). In most cases, the resulting device, often a single chip, is commonly referred to as a complete DDS or C-DDS. Practical DDS devices often integrate multiple registers to allow various frequency- and phase-modulation schemes to be realized. When included, the phase register’s contents are added after the phase accumulator. This enables the output sine wave to be phase-delayed in correspondence with a phase tuning word. This is extremely useful for phase-modulation applications in communication systems. The resolution of the adder circuit determines the number of bits in the phase tuning word and, therefore, the resolution of the delay. Integrating a DDS engine and a DAC in a single device has advantages and disadvantages, but whether integrated or not, a DAC is required to create a high quality analog signal of exceptional purity. The DAC converts the digital sine output into an analog sine wave and may be either single-ended or differential. A few of the key requirements are low phase noise, excellent wideband (WB-) and narrow-band (NB-)
A phase-locked loop is a feedback loop comprising: a Their inability to accurately and quickly tune the frequency output and waveform and their slow response limits their suitability for applications such as agile frequency hopping and some frequency- and phase-shift keying applications. Other approaches, including As a practical matter (see Table 2), rapid advances in CMOS processing, together with modern digital design techniques and improved DAC topologies, have resulted in the DDS technology achieving power consumption, spectral performance, and cost levels that were previously unattainable for a wide range of applications. While complete DDS products will never match the highest performance and design flexibility achievable with custom combinations of high-end DAC technology and FPGAs, the size-, power- and cost benefits, coupled with the simplicity of DDS devices, may make them easily the first choice for many applications.
Also note that since a DDS device fundamentally embodies a digital method of generating an output waveform, it can simplify the architecture of some solutions or make it possible to digitally program the waveform. While a sine wave is normally used to explain the function and operation of a DDS, it is easily possible to generate triangular or square (clock) wave outputs from modern DDS ICs, avoiding the need for a lookup table in the former case, and for a DAC in the latter case, where the integration of a simple yet precise comparator will suffice.
The f. In this example, where _{OUT}f = 25 MHz and _{CLOCK}f = 5 MHz, the first and second images occur (see Figure 3) at _{OUT}f × _{CLOCK}f, or 20 MHz and 30 MHz. The third and fourth images appear at 45 MHz and 55 MHz. Note that the sin(_{OUT}x)/x nulls appear at multiples of the sampling frequency. In the case where f is greater than the _{OUT}Nyquist bandwidth (1/2 f), the first image response will appear within the Nyquist bandwidth as an _{CLOCK}aliased image (a 15-MHz signal will alias down to 10 MHz, for example). The aliased image cannot be filtered from the output with a traditional Nyquist antialiasing filter.
In typical DDS applications, a low-pass filter is utilized to suppress the effects of the image responses in the output spectrum. To keep the cutoff requirements of the low-pass filter reasonable and the filter design simple, an accepted guideline is to limit the f frequency using an economical low-pass output filter._{CLOCK}The amplitude of any given image in response to the fundamental can be calculated using the sin( The amplitude of the first image is substantial—within 3 dB of the fundamental. To simplify filtering requirements for DDS applications, it is important to generate a frequency plan and analyze the spectral considerations of the image and the sin( f frequencies. Online interactive design tools supporting the Analog Devices DDS product family allow for quick and easy simulation of where images lie and allow the user to choose frequencies where images are outside the band of interest. See the _{CLOCK}Further Information and Useful Links section for additional useful information.Other anomalies in the output spectrum, such as integral and differential linearity errors of the DAC, glitch energy associated with the DAC, and clock feedthrough noise, will not follow the sin(
So choosing a stable reference clock oscillator with low jitter and sharp edges is critical. Higher frequency reference clocks allow greater oversampling, and jitter can be somewhat ameliorated by
- Communication and radar systems that require agile frequency sources for data encoding and modulation applications
- Measurement, industrial, and optical applications that require a generic frequency synthesis function with programmable tuning, sweeping, and excitation
In both cases, an increasing trend towards higher spectral purity (lower phase noise and higher spurious-free dynamic range) is coupled with low operating power and size requirements for remote or battery-operated equipment.
FSK) is one of the simplest forms of data encoding. The data is transmitted by shifting the frequency of a continuous carrier between one (binary 1, or mark) and the other (binary 0, or space) of two discrete frequencies. Figure 4 shows the relationship between the data and the transmitted signal.
Binary 1s and 0s are represented as two different frequencies, f0 and f1, respectively. This encoding scheme is easily implemented with a DDS device. The DDS frequency tuning word representing the output frequencies is changed so that f0 and f1 are generated from 1s and 0s to be transmitted. In at least two members of Analog Devices complete DDS product families (the AD9834 and the AD9838—see also the Appendix), the user can simply program the two current FSK frequency tuning words into the IC’s embedded frequency registers. To shift output frequency, a dedicated pin, FSELECT, selects the register containing the appropriate tuning word (see Figure 5).
More complex forms of PSK employ four or eight wave phases. This allows binary data to be transmitted at a faster rate per phase change than is possible with BPSK modulation. In four-phase modulation (
A reset must be initiated after power-up and before transferring any data to the DDS. This establishes the DDS output in a known phase, which becomes the common reference angle that allows synchronization of multiple DDS devices. When new data is sent simultaneously to multiple DDS devices, a coherent phase relationship can be maintained—or the relative phase offset between multiple DDS devices can be predictably shifted by means of the phase offset register. The AD983x series of DDS products have 12 bits of phase resolution, providing an effective resolution of 0.1°.
For more information about synchronizing multiple DDS devices, see AN-605 Application Note,
The information gathered on the response signal is used to determine key system information. The range of networks being tested (see Figure 7) can be quite wide, including cable integrity testing, biomedical sensing, and flow-rate measurement systems. Wherever the basic requirement is to generate frequency-based signals and compare phase and amplitude of the response signal(s) to the original signal, or if a range of frequencies needs to be excited through the system, or if test signals with different phase relationships (as in systems with I/Q capability) are required, direct digital synthesis ICs can be highly useful for digitally controlling stimulus frequency and phase through software with simplicity and elegance.
Other useful DDS information can be found on the DDS website. See also: Murphy, Eva and Colm Slattery. “All About Direct Digital Synthesis.” Ask The Applications Engineer—33.
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