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By Colm
Slattery, (colm.slattery@analog.com)
The load cell is inherently monotonic.
The main parameters of the load cell are
If the internal count needs to be 1:200,000 accurate for the full-scale range of 770 mV, the ADC therefore needs to be of the order of 3× to 4× better in order to meet the performance requirements. In this case, for a count of 1:800,000, the ADC would require 19 bits to 20 bits of accuracy. The practical challenge posed by the signal-processing requirement can now be understood.
Choosing the Best ADCThe best ADC architecture to use for weigh-scale applications
is sigma-delta, due to its low noise and its high linearity
at low update rates. A further benefit is that noise
shaping and digital filtering
are implemented on-chip. The integration in the high-frequency
modulator shapes the quantization noise so that the noise
is pushed toward one
half of the modulator frequency. The digital filter then
band-limits the response to a significantly lower frequency.
This greatly reduces
the need for complex post-processing of the ADC data
by the user.The ADC should also contain a low-noise programmable-gain amplifier (PGA) with high internal gain to magnify the small output signal from the load cell. An integrated PGA can be optimized to give low temperature drift, as compared to a discrete amplifier with external gain resistors. With a discrete configuration, any errors due to temperature drift will get amplified through the gain stage. The AD7799, specifically designed for weigh-scale applications, has an excellent noise specification (27 nV/rt-Hz) and a front-end gain stage with a maximum gain of 128 mV/mV. The load cell can be directly interfaced to this ADC. Figure 5 is a block diagram of a reference design, a weigh-scale system evaluation board designed at Analog Devices. It consists of an AD7799 ADC, controlled by an ADuC847 microcontroller. Besides providing the digital interface to the AD7799 and implementing the post processing, the ADuC847 microcontroller itself also contains a 24-bit, high-performance sigma-delta ADC. This will allow users to compare test results between a system containing the AD7799 ADC, and a completely self-contained system using the ADuC847 ADC, with the same hardware connections, so as to choose a design that best meets the requirements.
Figure
6 shows the measured data using the voltage reference as
the input to the ADC. The standard distribution of the
measured reference is 3.25 LSBs. Multiplying
this by 6.6 to calculate the peak-to-peak noise gives 21.65 LSBs. Converting
this into bits of resolution gives 4.42-bit noise. For a 24-bit ADC, this means
19.58 bits of “noise-free resolution.” Figure 7 shows the same test
completed on a typical load cell. The “noise-free resolution” in
this case is 19.4 bits. This means that the load-cell itself adds only 0.2 bits
of noise to the final result, so the ADC is shown as the principal contributor
of this noise.
An averaging filter is a good way to reduce random white noise while keeping the sharpest step response. The software for the design discussed here uses a moving-averaging algorithm. Figure 9 shows the basic algorithm flow.
A moving-average filter averages a number of points from the input signal to produce each point in the output signal. The input to the filter is taken directly from the ADC. Operating on the most recent M data points, the smallest and the largest data points (the outliers) are deleted from the data window. The remaining M – 2 points are averaged, as shown in the equation. Using the moving-average technique, the output data rate remains the same as the input data rate. This is first-order averaging. For higher update rates, second-order averaging is generally used to reduce the waveform dispersion. In that case, the output from the first stage is averaged through a second stage to further improve results. Figure 10 shows the measured data from the AD7799 after averaging. Comparing this to Figure 5: after averaging there is an improvement of about 2.3 bits in the final result (21.9-bit vs. 19.6-bit effective resolution). This technique can dramatically improve the final result, with no effect on LCD-output update rate. The only disadvantage of this technique is a longer settling time due to the pipeline delay of the averaging.
First, doubled judging steps are used in order to avoid taking a glitch as a weight change. When the differences between two continuous data points from the ADC and the output of the filter both exceed the threshold, this is considered as a weight change. All
In every display cycle, the software decides whether the displayed weight in this cycle is the same as the previous one. If it is the same, the LCD output will not change and the process continues to the next cycle. If it is different, the internal code difference between these two cycles will be calculated. If the difference is smaller than the threshold, it is regarded as noise effect, so the old weight will still be displayed. If the difference is bigger than the threshold, it will update the display.
Ratiometric DesignFor best performance, ratiometric measurement techniques
(same reference source for bridge excitation and ADC
reference) are employed in the reference design,
as in Figure 3. The output accuracy of the load cell is determined by the excitation
voltage of the bridge. The bridge output is directly proportional to the excitation
voltage, and any drift in the excitation voltage produces a corresponding drift
in the output voltage. By using a voltage that is proportional to the bridge
excitation voltage as the ADC’s reference source, there is no loss in measurement
accuracy if the actual bridge excitation voltage varies. This ratiometric connection
removes the effect of drifts and very low-frequency noise in the excitation source.
In order to filter out noise from the load cell at the inputs to the ADC, a simple
first-order RC filter can be used.
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