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ADN2855:  Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps Burst Mode Clock and Data Recovery IC with Deserializer

Product Details

The ADN2855 is a burst mode clock and data recovery IC designed for GPON/BPON/GEPON optical line terminal (OLT) receiver applications. The part can operate at 155.52 Mbps, 622.08 Mbps, 1244.16 Mbps, or 1250.00 Mbps data rates, selectable via the I2C interface.

The ADN2855 frequency locks to the OLT reference clock and aligns to the input data within 12 bits of the start of the preamble. The device provides a full rate or an optional half rate output clock for a double data rate (DDR) interface to an FPGA or digital ASIC.

All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. The ADN2855 is available in a compact 5 mm × 5 mm, 32-lead chip scale package.


  • Passive optical networks
  • GPON/BPON/GEPON OLT receivers

    • Serial data input
      155.52 Mbps/622.08 Mbps/1244.16 Mbps/1250.00 Mbps
    • 12-bit acquisition time
    • 4-bit parallel LVDS output interface
    • Patented dual-loop clock recovery architecture
    • Integrated PRBS generator
    • Byte rate reference clock
    • Loss-of-lock indicator
    • Supports double data rate (DDR)-compatible FPGA
    • I2C interface to access optional features
    • Single-supply operation: 3.3 V
    • Power
      670 mW typical in serial output mode
      825 mW typical in deserializer mode
    • 5 mm × 5 mm, 32-lead LFCSP

    Functional Block Diagram for ADN2855


    Title Content Type File Type
    ADN2855: Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps Burst Mode Clock and Data Recovery IC with Deserializer Data Sheet (Rev A, 02/2013) (pdf, 232 kB) Data Sheets PDF
    RAQs index Rarely Asked Questions HTML
    Why do I see reference spurs? FAQs/RAQs HTML
    Why is my phase noise shape changing when I change the PLL settings? FAQs/RAQs HTML
    Why doesn't the PLL make my reference input and the clock outputs line up? FAQs/RAQs HTML
    How do I optimize my PLL loop for the best phase noise and/or jitter? FAQs/RAQs HTML
    My loop is not locking. How do I debug this? FAQs/RAQs HTML
    How long does it take for the PLL to lock? FAQs/RAQs HTML
    Help! My PLL came unlocked over temperature. FAQs/RAQs HTML
    How do I choose between active and passive filter in PLL loop? FAQs/RAQs HTML
    Should I reference the passive filter to ground? or supply? FAQs/RAQs HTML
    How do the PLLs in the AD951x parts compare to other ADI PLLs? FAQs/RAQs HTML
    How does the clock clean-up function of the AD951x parts work? FAQs/RAQs HTML
    Why do I want to run a fast PFD frequency? FAQs/RAQs HTML
    Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins? FAQs/RAQs HTML
    Why can't I use a bandpass filter for my loop filter? FAQs/RAQs HTML
    Should I tie my loop filter to ground or PLL supply? FAQs/RAQs HTML
    The loop filter was working great until I changed the divide ratio in PLL. What happened? FAQs/RAQs HTML
    How do I use a VCO with a supply greater than 5V? FAQs/RAQs HTML
    What suppliers do you recommend for VCO/VCXOs? FAQs/RAQs HTML
    Do VCXOs have better phase noise and jitter performance than VCOs? FAQs/RAQs HTML
    How do I know which VCO will work best with the AD9510? FAQs/RAQs HTML
    Is there an advantage to running a higher VCO frequency than the output frequency? FAQs/RAQs HTML
    How do I determine if a VCO is good enough for my purpose? FAQs/RAQs HTML
    Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip? FAQs/RAQs HTML
    Do different divide ratios cause variations in jitter? FAQs/RAQs HTML
    I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips? FAQs/RAQs HTML
    Do divide ratios change the propagation delay? FAQs/RAQs HTML
    I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset? FAQs/RAQs HTML
    On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter? FAQs/RAQs HTML
    Why doesn't the mini-divider support the divide ratio I want? FAQs/RAQs HTML
    I want to use the variable delay adjust, but the jitter is too high. What can I do? FAQs/RAQs HTML
    I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on? FAQs/RAQs HTML
    What is the difference between the coarse phase adjust and the fine delay adjust? FAQs/RAQs HTML
    What is the fine delay adjust which is available on certain LVDS/CMOS outputs? FAQs/RAQs HTML
    Does the fine delay adjust affect the jitter? FAQs/RAQs HTML
    Why is the fine delay adjust not available on all the outputs? FAQs/RAQs HTML
    Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11? FAQs/RAQs HTML
    Will the AD9510 work without a reference input signal? FAQs/RAQs HTML
    What are the best clock sources for a distribution-only design? FAQs/RAQs HTML
    I am not using the CLK1 input on the AD9510. Can I just leave it floating? FAQs/RAQs HTML
    How good does my input signal need to be? FAQs/RAQs HTML
    I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked. FAQs/RAQs HTML
    Can I shift the threshold on clocks for single-ended inputs? FAQs/RAQs HTML
    The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510? FAQs/RAQs HTML
    Will differential or single-ended inputs/outputs improve my jitter? FAQs/RAQs HTML
    Why should I use differential rather than single-ended? FAQs/RAQs HTML
    How do I feed a single-ended signal into a differential input? FAQs/RAQs HTML
    Why do you recommend AC coupling, rather than DC coupling, at the clock inputs? FAQs/RAQs HTML
    Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts? FAQs/RAQs HTML
    Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs? FAQs/RAQs HTML
    On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate? FAQs/RAQs HTML
    I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong? FAQs/RAQs HTML
    Can I use the 951X clocks to drive a mixer (RF LO)? FAQs/RAQs HTML
    My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications? FAQs/RAQs HTML
    I have an input present at the clock input, but I'm not seeing an output? FAQs/RAQs HTML
    What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away? FAQs/RAQs HTML
    What clock frequency comes out of the AD9510 outputs when you first apply power to the device? FAQs/RAQs HTML
    Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF) FAQs/RAQs HTML
    I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz? FAQs/RAQs HTML
    What should I do with unused channels on the AD9510? FAQs/RAQs HTML
    Can I tri-state the AD9510 outputs? FAQs/RAQs HTML
    On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window? FAQs/RAQs HTML
    What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter? FAQs/RAQs HTML
    Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output? FAQs/RAQs HTML
    What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs? FAQs/RAQs HTML
    Does the AD9510 support 2.5V PECL? FAQs/RAQs HTML
    How much bandwidth is required to process a PECL or LVDS output? FAQs/RAQs HTML
    If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output? FAQs/RAQs HTML
    If I change the level of PECL output, does it affect the jitter? FAQs/RAQs HTML
    What is the best way to terminate LVPECL outputs to get lowest jitter? FAQs/RAQs HTML
    Is it okay to AC-couple PECL or LVDS outputs? FAQs/RAQs HTML
    What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs? FAQs/RAQs HTML
    What is the proper termination (value and location) for outputs? FAQs/RAQs HTML
    Are outputs short-circuit protected? FAQs/RAQs HTML
    Are the CMOS drivers on the clock devices complementary? FAQs/RAQs HTML
    Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)? FAQs/RAQs HTML
    I have pulled SYNCB low, but I still have output from a channel. Why? FAQs/RAQs HTML
    Why can I not get the same output amplitude or rise and fall times as stated in your datasheet? FAQs/RAQs HTML
    The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work? FAQs/RAQs HTML
    May I use the AD9540 for spread spectrum clocking? FAQs/RAQs HTML
    Can I get two clock outputs from the AD9540? FAQs/RAQs HTML
    What's the advantage of a DDS-based clock generator? FAQs/RAQs HTML
    Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter? FAQs/RAQs HTML
    I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications? FAQs/RAQs HTML
    On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong? FAQs/RAQs HTML
    How do you determine the bandwidth over which phase noise is integrated to obtain jitter? FAQs/RAQs HTML
    Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification? FAQs/RAQs HTML
    How do harmonic spurs in the output spectrum affect jitter (random or deterministic)? FAQs/RAQs HTML
    When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed? FAQs/RAQs HTML
    How do you specify jitter? FAQs/RAQs HTML
    How do I use the clock part for jitter clean-up? FAQs/RAQs HTML
    If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers? FAQs/RAQs HTML
    Does jitter vary with different clock frequencies? How about phase noise? FAQs/RAQs HTML
    I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts? FAQs/RAQs HTML
    Do you guarantee performance shown in ADIsimCLK? FAQs/RAQs HTML
    Who do I contact for technical support on ADIsimCLK? FAQs/RAQs HTML
    Should I use the minimum charge pump current settings in order to minimize power? FAQs/RAQs HTML
    Can I run CMOS outputs at 5V? FAQs/RAQs HTML
    Can I use different power supply voltages for the PECL output drivers? FAQs/RAQs HTML
    Is .01 uF sufficient for power supply pin bypass? FAQs/RAQs HTML
    My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power? FAQs/RAQs HTML
    Why don't you spec psrr and cmrr in the datasheet? FAQs/RAQs HTML
    How do I get two AD951x (with PLL) to synchronize to the same reference input edge? FAQs/RAQs HTML
    I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN? FAQs/RAQs HTML
    How do I synchronize multiple clock devices? FAQs/RAQs HTML
    What happens if I run the part in an ambient environment which exceeds 85°C? FAQs/RAQs HTML
    How can I determine the die temperature of your device? FAQs/RAQs HTML
    My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND? FAQs/RAQs HTML
    What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package? FAQs/RAQs HTML
    Glossary of EE Terms Glossary HTML

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    ADN2855 Evaluation Board
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