The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements.
There are four independent differential clock outputs, each with types of logic levels available. Available logic types include LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8V CMOS (250 MHz). In 1.8V CMOS output mode, the differential output becomes two CMOS single ended signals. The CMOS outputs are 1.8V logic levels regardless of the operating supply voltage.
Each output has a programmable divider that can be bypassed or be set to divide by any integer up to 1024. In addition, the AD9508 supports a coarse output phase adjustment between the outputs.
The device can also be pin-programmed for various fixed configurations at powered up without the need for SPI or I²C programming.
The AD9508 is available in a 24-lead LFCSP and can be operated from a either a single 3.3 V or 2.5 V supply. The temperature range is −40°C to +85°C.APPLICATIONS
|Title||Content Type||File Type|
|AD9508: 1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust Data Sheet (Rev C, 02/2014) (pdf, 1422 kB)||Data Sheets|
|Multi-output, 1.65-GHz Clock Buffer and Divider Delivers Low Jitter to Optimize Noise Performance in Ultra-high-speed Data Converters (13 Feb 2013)||Press Releases||HTML|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
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