MXD1005
5-Tap Silicon Delay Line
Overview
- Improved Second Source to DS1005
- Available in Space-Saving 8-Pin µMAX Package
- 17mA Supply Current vs. Dallas' 40mA
- Low Cost
- Delay Tolerance of ±2ns or ±3%, whichever is Greater
- TTL/CMOS-Compatible Logic
- Leading- and Trailing-Edge Accuracy
- Custom Delays Available
The MXD1005 silicon delay line offers five equally spaced taps with delays ranging from 12ns to 250ns and a nominal accuracy of ±2ns or ±3%, whichever is greater. Relative to hybrid solutions, this device offers enhanced performance and higher reliability, and reduces overall cost. Each tap can drive up to ten 74LS loads.
The MXD1005 is available in multiple versions, each offering a different combination of delay times. It comes in the space-saving 8-pin µMAX package, as well as an 8-pin SO or DIP, allowing full compatibility with the DS1005 and other delay line products.
Applications
- Clock Synchronization
- Digital Systems
Documentation
Data Sheet 1
This is the most up-to-date revision of the Data Sheet.
Software Resources
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