ADN2811

Obsolete

OC-48/OC-48 FEC Clock and Data Recovery

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Overview

  • Meets SONET requirements for jitter transfer/generation/tolerance
  • Quantizer sensitivity: 4 mV typical
  • Adjustable slice level: ±100 mV
  • 1.9 GHz minimum bandwidth
  • Patented clock recovery architecture
  • Loss of signal detect range: 3 mV to 15 mV
  • Single reference clock frequency for both native SONET and 15/14 (7%) wrapper rate
  • Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK
  • LVPECL/LVDS/LVCMOS/LVTTL compatible inputs (LVPECL/LVDS only at 155.52 MHz)
  • 19.44 MHz on-chip oscillator to be used with external crystal
  • Loss of lock indicator
  • Loopback mode for high speed test data
  • Output squelch and bypass features
  • Single-supply operation: 3.3 V
  • Low power: 540 mW typical
  • 7 mm × 7 mm, 48-lead LFCSP
ADN2811
OC-48/OC-48 FEC Clock and Data Recovery
ADN2811 Functional Block Diagram ADN2811 Pin Configuration
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Data Sheet 1

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