The ADN4670 is a low voltage differential signaling (LVDS) clock driver that expands a differential clock input signal to 10 differential clock outputs. The device is programmable using a simple serial interface, so that one of two clock inputs can be selected (CLK0/CLK0 or CLK1/CLK1) and any of the differential outputs (Q0/Q0 to Q9/Q9) can be enabled or disabled (tristated). The ADN4670 is designed for use in 50 Ω transmission line environments.
When the enable input EN is high, the device may be pro-grammed by clocking 11 data bits into the shift register. The first 10 bits determine which outputs are enabled (0 = disabled, 1 = enabled), while the 11th bit selects the clock input (0 = CLK0, 1 = CLK1). A 12th clock pulse transfers data from the shift register to the control register.
The ADN4670 is fully specified over the industrial temperature range and is available in a 32-lead LFCSP package.
|Title||Content Type||File Type|
|ADN4670: Programmable Low Voltage 1:10 LVDS Clock Driver (Rev A, 01/2012) (pdf, 164 kB)||Data Sheets|
|AN-1176: Component Footprints and Symbols in the Binary .Bxl File Format (pdf, 671 kB)||Application Notes|
|AN-1177: LVDS and M-LVDS Circuit Implementation Guide (pdf, 586 kB)||Application Notes|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
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