The ADN2917 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 8.5 Gbps to 11.3 Gbps. The ADN2917 automatically locks to all data rates without the need for an external reference clock or programming. ADN2917 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance.
The ADN2917 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier or equalizer at the input. The equalizer is either adaptive or can be manually set.
The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers.
The ADN2917 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. The ADN2917 is available in a compact 4 mm × 4 mm, 24-lead frame chip scale package (LFCSP). All ADN2917 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted.
|Title||Content Type||File Type|
|ADN2917: Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ Data Sheet (Rev 0, 05/2014) (pdf, 708 kB)||Data Sheets|
|Glossary of EE Terms||Glossary||HTML|
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