The ADN2915 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automatically locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance.
The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer, or bypass at the input. The equalizer is either adaptive or manually adjustable .
The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers.
The ADN2915 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features.
The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2915 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted.
|Title||Content Type||File Type|
|ADN2915: Continuous Rate 6.5 Mbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ Data Sheet (Rev 0, 07/2013) (pdf, 352 kB)||Data Sheets|
|UG-551: XStream™ ADI-BERT: An 11.3 Gbps Bit Error Rate Tester Solution Based on ADN2915, a Continuous-Tuning Wideband Clock and Data Recovery IC (pdf, 1884 kB)||User Guides|
|Glossary of EE Terms||Glossary||HTML|
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