Product Details

This implementation of the MPEG-2 Video Encoder has been highly optimized to run on the Analog Devices ADSP-BF5xx Blackfin processor. It is a self-contained software module that is fully compliant with ISO/13818-2, Information technology - Generic coding of moving pictures and associated audio information: Video, Second edition 2000-12-15, specification.

The code has been implemented using Instruction and Data cache. To optimize video encoding performance, internal SRAMs for Program and Data memory and Memory DMA are also utilized effectively.

Features

  • Profiles: Simple Profile and Main Profile
  • Frame types supported: I & P
  • Input Resolution: Up to 5 Mega Pixel, D1 inclusive
  • Entropy Encoder: VLC
  • Motion vector resolution: Half pixel
  • Pre-Processing: A simple 2:1 and 4:1 downscaling and de-interlacing for YUV420 and YUV422 format Pre-processing API to enable applications to plug-in own pre-processing blocks into encoder
  • Scene Change Detection: Supported
  • Scalability: Scalable Search Engine for MIPS and Quality trade-off
  • Number of Reference Frames: 1
  • Cache: Different configurations; No Cache and All Cache
  • ROI : Region of Interest Encoding Support for YUV420 and YUV422 input formats
  • ADSP-BF561 core loading: Symmetrical or Asymmetrical loading across core-A and core-B
  • Macroblock level quantization: Enabled for better rate control
  • Bitrate control: VBR and CBR. Flexibility of switching between VBR and CBR during encoding
  • Both NTSC & PAL format supported
  • Max Output Resolution: ADSP-BF561: Up to D1 at 30fps; 5MPixel at lower fps ADSP-BF533: up to 1/2 D1 at 30fps; D1 at 15fps; 5Mpixel at lower fps
  • Conformance Standard: INTERNATIONAL STANDARD ISO/IEC13818-2:2000, Second edition 2000-12-15
  • Target Processor: ADSP-BF533, ADSP-BF561, ADSP-BF527, ADSP-BF548, code compatible across the Blackfin processor family ADSP-BF5xx
  • Release format: Object code module with C source wrapper
  • Input format: ITU-R BT.656 format or YUV420 planar format or YUV422 progressive format from CMOS sensors

System Requirements

  • Windows XP Professional SP3 (32-bit only).
  • Windows Vista Business/Enterprise/Ultimate SP2 (32-bit only). It is recommended to install the software in a non-UAC-protected location.
  • Windows 7 Professional/Enterprise/Ultimate (32 and 64-bit). It is recommended to install the software in a non-UAC-protected location.
  • Minimum of 2 GHz single core processor, 3.3 GHz dual core is recommended.
  • Minimum of 1 GB memory (RAM), 4 GB is recommended.
  • Minimum of 2 GB hard disk (HDD) space is required.

Related Hardware

  • Hardware: Evaluation board/Evaluation version of VisualDSP++
  • Processor: This Software Module supports the ADSP-BF561, ADSP-BF52x, ADSP-BF54x, ADSP-BF52x processor families.
  • Demonstrations are available on ADSP-BF533, ADSP-BF561, ADSP-BF527, ADSP-BF548 EZ-KIT Lites. Note that the BF535 is not supported.

Any of the following combinations of hardware can be used to run the demo application provided in the release package.

Performance Metrics

  MIPS/Memory summary table:
  Main Profile:

Code memory (KB) Data RAM (KB) Frame Buffer (MB) Output Buffer (MB) Input Buffer (MB) Cycles/pel
Average Moving Average Peak
51.39 26.12 1.41 1.00 1.08 80 (830) 86 (880)

  • MIPS measured using a bit rate of 6.0Mbps, 30 fps, 720x480 (NTSC D1) image size, ITU-R BT.656 input, NTSC format, optimal memory layout, ADSP-
  • BF561 rev 0.5 processor, for Main Profile.
  • Measurements done with CAS1 =3 for SDRAM, CCLK2 =600, SCLK3 =120 for ADSP-BF561.
  • Data cache and instruction cache are enabled. The cache is set in "write back" and "small cache" (DCBS=0) mode.
  • Memory DMA is used with 32 bit DMA.
  • "Data RAM" for one instance includes Stack, Scratch, Encoder Instance Memory, for D1 PAL resolution.
  • Frame Buffer for one instance of encoder and D1 PAL resolution.
  • Minimum Input and Output Single Buffers, for ITU-R BT656 D1 PAL input.
  • 1 MB = 1024 KB; 1 KB = 1024 Bytes.
  • NOTE: In deriving the "Moving Avg Peak" value, an 8 consecutive frame sliding window was used.
  • An average cycle count was measured for each window of frames, and the worst case average cycle from all the sliding window measurements was determined to be the "Moving Avg Peak" value.

CAS1 – Column Address Strobe Latency. Please refer BF5xx Hardware Reference Manual for more details on CAS.
CCLK2 – Core clock
SCLK3 – System Clock

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Availability and Licensing

Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.

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