This implementation of the MPEG-2 Video Encoder has been highly optimized to run on the Analog Devices ADSP-BF5xx Blackfin processor. It is a self-contained software module that is fully compliant with ISO/13818-2, Information technology - Generic coding of moving pictures and associated audio information: Video, Second edition 2000-12-15, specification.
The code has been implemented using Instruction and Data cache. To optimize video encoding performance, internal SRAMs for Program and Data memory and Memory DMA are also utilized effectively.
Any of the following combinations of hardware can be used to run the demo application provided in the release package.
MIPS/Memory summary table:
|Code memory (KB)||Data RAM (KB)||Frame Buffer (MB)||Output Buffer (MB)||Input Buffer (MB)||Cycles/pel|
|Average||Moving Average Peak|
|51.39||26.12||1.41||1.00||1.08||80 (830)||86 (880)|
CAS1 – Column Address Strobe Latency. Please refer BF5xx Hardware Reference Manual for more details on CAS.
CCLK2 – Core clock
SCLK3 – System Clock
Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.