The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.
For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a pixel clock from HSYNC and COAST; midscale clamping; and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.
The on-chip PLL of the AD9888 generates a pixel clock from the HSYNC and COAST inputs. Pixel clock output frequencies range from 10 MHz to 170 MHz. PLL clock jitter is typically less than 450 ps p-p at 170 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabled, and an external clock input can be provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications.
A CLAMP signal is generated internally or can be provided by the user through the CLAMP input pin. This device is fully program-mable via a 2-wire serial port.
Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving, 128-lead, MQFP, surface-mount, plastic package and is specified over the 0°C to 70°C temperature range. The AD9888 is also available in a Pb-free package.
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|AD9888: 100/140/170/205 MSPS Analog Flat Panel Interface Data Sheet (Rev C, 12/2011) (pdf, 502 kB)||Data Sheets|
Analysis of Common Failures of HDMI CT
By Brett Li and Lie Dou, ATV Product Line, Analog Devices
(Digital TV DesignLine, 4/2/2008)
|AD9888: Analog Interface for Flat Panel Displays (pdf, 61 kB)||Overview|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
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CCD Pll Settings
These spreadsheets help with the programming of the on-chip PLL on the AD988x flat panel display devices. They will help generate the pixel clock and optimize the performance of the PLL for many of the different industry standard video formats.
|AD9888 IBIS Models||IBIS Models||HTML|
Symbols and Footprints— Analog Devices offers Symbols & Footprints which are compatible with a large set of today’s CAD systems for broader and easier support.
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