A comparator is a fundamental analog building block which can be used to determine whether an input voltage is higher or lower than a reference voltage, and set the output to one of two levels. Comparators can be used in a wide range of applications, such as high speed trigger circuits, clock and data recovery, and 1-Bit analog-to-digital conversion. Comparators are also key components in many industrial wideband data acquisition, ATE, and real time medical imaging systems. In these systems, the common design trend is to simplify the complexity of all of the stages from signal acquisition to analog-to-digital conversion (ADC), resulting in digitization of signals at higher sample rates. Consequently, many traditional comparator circuits are now operating at higher clock and data rates, and this has resulted in more stringent specifications for random and deterministic jitter, lower propagation delay, reduced data skew values and even lower power consumption.
To meet these requirements Hittite Microwave now offers a full line of high speed, low power comparators for use in the above mentioned applications. Hittite’s comparators currently include six products, which can be sub-divided into two categories: the level-latched family which includes part numbers HMC674LC3C, HMC675LC3C and HMC676LC3C; and the clocked or edge-latched family which includes part numbers HMC874LC3C, HMC875LC3C, and HMC876LC3C. Both families share the same proven input topology that offers the advantage of high input bandwidth (>10 GHz), low propagation delay dispersion, low jitter, and high input-common-mode-range. At the same time, both families maintain very low power and low thermal hysteresis. Figure 2 highlights the topology differences between the two families. Devices from both families are offered with reduced output swing ECL, PECL, and CML logic driver versions. Table 1 compares the key specifi cations of both families.
|Parameter||Level-Latched Family||Clocked Family||Units|
|Equivalent Input BW||10||10||GHz|
|Input Clock Rate||n/a||20||Gbps|
|Tpd (Propagation Delay)||85||120||ps|
|Tpd Dispersion for 50 mV < VOD < 1 V||10||10||ps|
|Tpd Dispersion for –1.75 V < Vcm < +1.75 V||8||8||ps|
|Minimum Input Pulse Width (VOD = ±100 mV)||60||60||ps|
|Deterministic Jitter (p-p)||2||< 3||ps|
|Random Jitter (rms)||0.2||0.2||ps|
|Input CM||–1.75 to +1.75||–1.75 to +1.75||V|
|Power Dissipation (Pd)||100 - 140||130 - 150||mW|
|LE/LE Pins Termination||8000
(High Impedance to all track only)
|Hysteresis Control||0 to 25||0 to 25||mV|
Level-Latched Comparator Family
HMC674LC3C, HMC675LC3C and HMC676LC3C are monolithic, fast comparators which feature latch inputs and reduced swing PECL, CML and ECL output drivers respectively. These comparators support 10 Gbps operation and exceed the performance of their closest competitors by providing approximately double the speed with almost 50% reduction in power dissipation. The HMC67xLC3C comparator family also exhibits 85 ps propagation delay and 60 ps minimum pulse width with only 0.2 ps rms jitter (RJ).
The most important characteristic of a comparator is to preserve the phase and timing information at the instant that the input voltage crosses the reference. Any aberration of this instant is due to dispersion and jitter which results in distortion of the phase/timing information. The ability to latch this information is important in noisy environments or when the user is interested in a timing window for the threshold crossing.
The level-latched comparator family also offers several application-specific options to the user. First, the latch pins (LE/LE) can be left floating (see Figure 2), such that the comparator is in the unlatched or transparent mode. This feature is useful for temporal alignment, which is a critical requirement in MRI or medical ultrasound applications. The high gain of the comparator allows the user to detect whether the input level has exceeded the reference level without requiring additional amplification prior to the output stage. No additional LE/LE voltage is required for these applications.
If the LE/LE latch pins are driven, then the comparator can attain its latched phase. In this mode, the user can store (or latch) the actual crossover instant. The comparator remains in the latched mode when the LE voltage level exceeds the LE voltage level. To reverse to the transparent mode the voltage levels are reversed, (i.e. the LE voltage level is less than the LE voltage level).
The level-latched comparators have been optimized to significantly reduce thermal hysteresis. In some applications however, the differential input to the comparator may be superimposed on a slow varying signal, which could cause the comparator to “chatter.” In those applications, it is beneficial for the user to create a known amount of hysteresis (non-thermal). The level-latched comparator family accomplishes this by connecting the HYS pin through a resistor to the negative terminal (Vee). The amount of hysteresis may be programmed from 0 to 25 mV by selecting the appropriate resistor value, as shown in Figure 3.
One of the most important characteristics of any comparator is propagation delay - the time required for the output to switch from a low state to a high state, when the input voltage crosses the reference level. A more critical issue however, is the change in propagation delay as a function of overdrive voltage (VOD). This change in propagation delay is called dispersion, as shown in Figure 4. Hittite’s comparators exhibit minimal dispersion, which is highly beneficial in applications where phase preservation is critical.
Equally important for a comparator is its ability to accept a large common mode voltage at its input without affecting the propagation delays. Hittite’s comparators can accept input common mode voltages between +1.75 to –1.75V, which makes them ideal for a wide range of applications (Figure 5).
Finally, jitter is an important parameter of the comparator as it characterizes the variation in response time over a large number of sampled input voltages. This is especially important in ATE channels where any source of noise can contaminate the desired information. Figure 6 shows a typical eye diagram of Hittite level-latched comparators.
The level-latched comparators are housed in compact, ceramic, RoHS-compliant, 3 × 3 mm SMT packages and are specified for operation from –40°C to +85°C.
The Clocked Comparator Family
The clocked comparator family is unique in the market today, offering 20 Gbps speed at 150 mW power consumption, which represents 50% less power than traditional comparator solutions. The HMC874LC3C, HMC875LC3C and the HMC876LC3C are monolithic, ultra fast clocked comparators that are ideal for ATE and medical imaging applications where high speed, high performance and low power are critical requirements.
The clocked comparator family is an extension of the level-latched family, and it relies on the same input front end circuit. The additional latch inserted between the first latch and the output stage (Figure 2) changes the latching instance from a voltage level to an edge of the clock signal.
Consider the application of a latch signal applied to the level-latched comparator. If the signal has a 50% duty cycle, then the timing allowed for the comparison of the input and the threshold voltage is half of this period (during the other half of the period, the device is in its latched phase). In contrast to the level-latched comparator, the edge-latched comparator accomplishes the latching function on the rising edge of the clock. This is advantageous since an entire clock period can now be dedicated to the next comparison phase.
Unlike the level-latched comparators, the CLK/CLK ports of the clocked comparators are terminated with 50 Ω resistors, so these pins cannot be left floating to create a transparent (unlatched) mode.
However, all other features of the level-latched family are either maintained or improved. The clocked comparator family features high input bandwidth of 10 GHz, low propagation delay dispersion of 10 ps, low random jitter of 0.2 ps, and high input-common-mode-range of ±1.75V. Clock-to-data output delay is specified at only 120 ps.
Although the clocked comparator family is normally specified to operate with clocks of 20 GHz, up to 25 GHz can be achieved if logic output swings lower than 300 mV are acceptable.
The clocked comparators are housed in compact, ceramic, RoHS-compliant, 3 × 3 mm SMT packages and are specified for operation from –40 °C to +85 °C.
Hittite Microwave continues to lead the way with state-of-the-art innovations in high speed, low power comparator components.
The level-latched and clocked comparator families were developed to be used in applications where speed/power dissipation is defined as an important figure of merit. The larger the ratio, the better these comparators are suited to the task. For example, in an ATE system, thousands of comparators may be required, so power comes at a large premium. Similar requirements arise in the medical field (MRI/Ultrasound) even though the bandwidth requirements are reduced. Clearly, low dispersion vs. input slew and overdrive conditions as well as low jitter is important in medical equipment applications as it translates to low noise since the frequency used in penetrating different tissue depths is varied. The low dispersion vs. overdrive specification allows the multi-channel sensors to be aligned temporally and therefore require fewer calibration cycles.
Designers looking for versions of these products with alternate pinouts, alternate DC power supply voltages or higher operating speeds should contact Hittite Microwave directly. Multiple comparator and/or logic functions may also be combined to provide products with higher levels of integration, and these may be made available in SMT packages or module format to meet the needs of custom applications. Data sheets and supporting information for Hittite’s comparators are available at www.hittite.com.