Passing EMI Compliance Testing the First Time—Part 3: From Schematic to Placement and Grounding Architecture

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Figure 1

   

要約

The first two parts of this series established the fundamental physics of field confinement on a PCB and presented practical layout techniques for minimizing electromagnetic interference (EMI), interference, and susceptibility to external fields. Part 3 of this series addresses the critical early decisions that determine the success of any complex board layout: how to translate schematic intent into a sound placement strategy, and how to choose the right grounding architecture before routing begins. It examines how to organize the schematic for layout readiness, how to use differential signaling to preserve ground fidelity, and when to select a ground tree over a solid ground plane. Getting these foundational decisions right from the start is the surest path to a board that passes EMI compliance the first time.

Introduction

Starting a layout only to discover midway through that there are not enough layers to complete the job correctly is a common challenge. How should a layout be floor planned for a complex board to avoid the possibility of needing to start over? Part 3 of this series will address the foundational planning questions that must be answered before routing can begin.

• How much physical area (generally related to the number of parts and pins) is needed to complete the layout correctly?
• How is the schematic itself used to drive placement decisions and avoid interference before a trace is routed?
• When does a design call for a ground tree rather than a ground plane?

There are online resources to help estimate the PCB area and number of signal layers required. Most will ask for the following information.

• What is the total number of components and pins?
• What is the via annular ring and drill size?
• What is the minimum trace width allowable?
• What is the functional voltage spacing requirement?

These online tools are helpful but not sufficient. Most do not consider heat flow requirements, current capacity for some nets, increased voltage spacing due to functional or safety spacing requirements, or the additional design techniques and spacing needed to avoid crosstalk for especially sensitive circuitry. In short, they do not know anything about the actual application.

This article will provide a procedure to use as a guide to help design a better PCB.

Schematics to Placement

The schematic always comes first, and the designer should understand everything about the schematic and how the circuit works from the inside out. This point cannot be overemphasized.

As stated earlier, the area and dimensions of the board generally depend on the number of parts and pins, while the stack-up is defined by the number of nets or transmission lines and their function. The schematic (or the design) should define these constraints, but this is not always the case—occasionally there is only so much space available. Place components on the schematic in a way that reflects the need in the layout, or at least make notes in the schematic to help with this. Nodes that need to be small can be small (or noted so) on the schematic and circuits that need to be close should be close on the schematic. These techniques will help when placing parts. Some designs (RF or high-speed digital) care about physical distances (propagation delays) or for other analog reasons (precision analog, for example), while for other designs, circuit components can be considered as lumped elements, for which the physical distances do not matter. All these details can be noted on the schematic in some way to show what is important when going from the schematic to the board.

Placing and Routing Parts

To a certain extent, layout options will also influence the schematic. This is often the case when needing to overcome compromises arising from a low layer count board, or the need for a multiboard design (including board-to-board connectors). One example of this is the need for differential signaling (Figure 1). This technique is commonly used for analog or digital signals that need to span a long distance, such as in a cable. In this technique, both positive and negative signals are sent down the cable (in addition to the ground). The displacement current from each of the signals will sum to zero in the ground, resulting in a communication path virtually immune to common-mode interference or electromagnetic interference (EMI) generation. The same technique can be used over shorter distances on the PCB to preserve the fidelity of the ground for precision or sensitive analog or when PCB distances become too long.

In Figure 1a, two complementary signals of equal length are run together sharing the same ground plane. In Figure 1b, the signal lines are placed on different layers separated by the ground plane. Since the physical location for each signal is nearly identical, any interference signals coupled should also be identical. This means that the differential signal will reject the coupled noise.

Sometimes it is simply not possible to eliminate current in the ground and, when this is the case, it becomes necessary to either separate the ground plane into sections or to run a ground tree instead. The necessity of this depends on the geometry of the layout. To help with this, modify the schematic to separate the grounds—same net, just use different ground symbols gnd1, gnd2, gnd3, etc.—to force separation of these on the layout.

The Ground Tree vs. the Ground Plane

As stated in Part 2, nature always plans to take the least energy (stored or dissipated) from the source. For AC signals on tracks over a ground plane, this means that the signal ground return current will always run in the ground directly under the signal trace. Faraday’s law should single-handedly serve the purpose of containing the fields, yet there is an entire ground plane (or two for strip-line designs) surrounding the signal trace. Solid ground planes provide better high-frequency decoupling (a lower impedance source of power at higher frequencies), and all that copper just does a better job containing DC and AC fields.

So why use a ground tree structure instead of a ground plane? Figures 2 and 3 illustrate both methods, alongside the equation describing the impedance of a lossy transmission line,

Looking at the equation first, at DC (ω = 0) note that the impedance of the line is √(R/G)(the lossy part). For the current return, 1/G is also a resistance so the current returns by the path of least resistance, utilizing all available copper. Nature is just minimizing energy. In this low-frequency case, much more energy would be dissipated in I2R losses than would be stored in the ground loop inductance. For ω = 0, the DC return current will no longer be confined to the space directly under the signal trace, and current flow in copper translates to drops of voltage on the ground plane.

Begin the ground tree at the transformer returning the highest noisiest currents first (Figure 2). From here, continue adding ground return currents to the branch ending with the measurement grounds. This method transforms ground noise and errors to a common-mode signal that is easy to reject. Note: Some branches may be long to accommodate the component location. Ground fill can be applied to all branches at the end to lower the supply impedance without compromising the method.

Begin by dedicating each side of the ground plane as the return path for the adjacent signal layer. Without the advantages of the ground tree, the parts placement will define whether a ground current noise source will transform into a common-mode or a normal-mode error at low frequencies.

Alternatively, at higher frequencies, inductance prevents the overall current from being high, so storing less energy becomes the important parameter to minimize the energy taken from the source.

At low frequencies, voltage drops in the ground from this current can induce measurement errors, depending on parts placement and where critical measurements reference ground. Ground, it would seem, may not take a value of zero everywhere.

Next, consider the ground plane arrangement shown in Figure 3. This method controls the location of return currents so that high currents cannot cause drops that would be measured.

In the schematic, each branch could be labeled differently, helping to enforce the architecture in the PCB. Really, using the ground tree is much more work in layout since containing AC fields is still required by providing a controlled (and small) field space for all transmission lines. All that copper fill shown in Figure 2 is needed to solve this problem.

Conclusion

The decisions made before a single trace is routed determine the success of everything that follows. By organizing the schematic to reflect the demands of the layout, and choosing the correct grounding architecture early, the groundwork is laid for a board that will perform as intended. Whether the design calls for a solid ground plane or a carefully controlled ground tree, the goal remains the same: confine the fields, control the return currents, and prevent noise from reaching sensitive nodes. Part 4 of this series will build on this foundation, addressing how to plan and route the power system and how to arrive at the correct layer count and stack-up for your design.

References

Feynman, Richard P., Robert B. Leighton, and Matthew Sands. The Feynman Lectures on Physics, Vol. 2: The New Millennium Edition: Mainly Electromagnetism and Matter. Basic Books, 2011.

Johnson, Howard W. and Martin Graham. High-Speed Digital Design: A Handbook of Black Magic. PTR Prentice Hall, April 1993.

Morrison, Ralph. Fast Circuit Boards: Energy Management. John Wiley & Sons Publications, January 2018.

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