MAXREFDES1016

The MAX17509 integrates two 3A internal switch stepdown regulators with programmable features. The device can be configured as two single-phase 3A power supplies or as one dual-phase, single-output 6A power supply. It operates from a 4.5V to 16V input and generates independently adjustable output voltage in the ranges of 0.904V to 3.782V and 4.756V to 5.048V, with ±2% system accuracy. This device provides maximum flexibility to the end-user by allowing to choose multiple programmable options by connecting resistors to the configuration pins. Two key highlights of the device are the self-configured compensation for any output voltage and the ability to program the slew rate of LX switching nodes to mitigate noise and EMI concerns. Noise-sensitive applications, such as high-speed multi-gigabit transceivers in FPGAs, RF, and audio applications, can benefit from this unique slew-rate control. SYNC input is provided for synchronized operation of multiple devices with system clocks.

The MAX17509 offers output overvoltage (OV) and undervoltage (UV) protection, as well as overcurrent (OC) and undercurrent (UC) protection with a selectable hiccup/latch option.

• Reduces Number of DC-DC Regulators in Inventory
• Output Voltage (0.904V to 3.782V and 4.756V to 5.048V with 20mV Resolution)
• Configurable Two Independent Outputs (3A/3A) or a Dual-Phase Single Output (6A)
• Mitigate Noise Concerns and EMI
• Adjustable Switching Frequency with Selectable 0/180° Phase Shift
• External Frequency Synchronization
• Adjustable Switching Slew Rate
• Passes EN55022 (CISPR22) Class-B Radiated and Conducted EMI Standard
• Ease of System Design
• All Ceramic Capacitors Solution
• Auto-Configured Internal Compensation Selectable Hiccup or Brick-Wall Mode
• Adjustable Soft-Start Rise/Fall Time with Soft-Stop Modes and Prebias Startup

A dual-phase buck converter using MAX17509 is demonstrated for a 1.1V DC output application. The power supply delivers up to 6A at 1.1 V. Table 1 shows an overview of the design specification.

This document describes the hardware shown in Figure 1. It provides a detailed systematic technical guide to design in a dual-phase buck converter using Maxim’s MAX17509 step-down DC-DC converter. The power supply has been built and tested, details of which follow later in this document.

The main components of a buck converter are the power switch, which usually comes in the form of a MOSFET, the inductor, and the diode. As the MOSFET is switched on and off, a magnetic field is generated in the inductor. When the switch is on (or closed), current flows into the inductor and through the output. When the switch is off (or open), due to the magnetic field, current still flows from the inductor to the output load.

When the transistor switch is on, it supplies the output load with current. Initially, current flow to the load is restricted as energy is also being stored in the inductor. The current in the load and the charge on the output capacitor therefore build up relatively slowly in comparison with the switch-on time of the MOSFET. During the on period there is a large voltage across the diode, which causes it to be reverse-biased.

When the transistor switch is off, the energy that had been stored in the inductor’s magnetic field is released. The voltage across the inductor is now in reverse polarity, and sufficient stored energy is available to maintain current flow while the transistor is open. The reverse polarity of the inductor allows current to flow in the circuit via the load and the diode, which is now forward-biased. Once the inductor has been drained of the majority of its stored energy, the load voltage begins to fall, and the charge stored in the output capacitor then becomes the main source of current. This leads to the ripple waveform shown in Figure 2.

For low-voltage/high-current applications, high efficiency and low power dissipation is the main requirement. Multiphase buck converters are those where two or more inductor phases are connected to share the output current. In multiphase converters, the phases are interleaved by 180° (dual phase) or 120° (three phase), etc.

Proper interleaving of the phases reduces the input, and output ripple-current stress ensures high efficiency by equally sharing the load current. The dissipation in MOSFETs is also reduced if a dual-phase converter is used. See Figure 3.

A power solution using the MAX17509 can be configured completely by using seven configuration pins. These configuration pins include the following:

• MODE
• SS1
• SS2
• COARSE1
• COARSE2
• FINE1
• FINE2

To recognize the resistance value reliably, we used standard 1% resistors between the configuration pins and SGND.

The MODE pin chooses between single-phase (two outputs) and dual-phase (one output), sets the relative phase-shift of the PWM between two regulators, and sets the internal switching frequency. SS1 chooses between brick-wall and latchoff and hiccup modes for the OCP behavior of both regulators. It also enables/disables softstop and sets soft-start time for Regulator 1. SS2 chooses between the maximum and minimum LX-slew rate of both regulators. It also enables/disables soft-stop and sets soft-start time for Regulator 2. The configuration pins can respond to both pin strapping and resistor programming. There are 16 possible selections of configuration pins and these settings are summarized in Table 2. This table also shows a correspondence between the resistor values to the index numbers.

Step 1: Switching Frequency

The MAX17509 supports a selectable switching frequency of either 500kHz, 1MHz, 1.5MHz, or 2MHz for input supply rails up to 6V. For supply rails greater than 6V, the switching frequency can be programmed only to 1MHz. High-frequency operation optimizes the application for the smallest component size, lower output ripple, and improve transient response, but trading off efficiency to higher switching losses. For our design, we use a 1MHz switching frequency, f_SW = 1MHz.

Step 2: MODE Selection

The MODE pin is used to configure the MAX17509 to produce a dual-phase single-output regulator. In dual-phase mode, the two phases operate to supply a shared output current up to 6A with 180° relative phase shift of PWM. Inductors selected must be the same for the phases to ensure current balance. The EN pins of the two phases should be connected together.

For our dual-phase design at 1MHz, Table 2 gives us the required value of R_MODE as R_MODE = 15kΩ.

How Table 2 should be used for this selection is shown in Table 3 by yellow highlighted text.

Step 3: Overcurrent Behavior

The current-protection circuit monitors the output current levels through internal high-side and low-side MOSFETs during all switching activities to protect them during overload and short-circuit conditions.

Peak positive current limit (OC) occurs when load requirement is greater than regulator capability. Valley negative current limit (UC) can occur when the regulator sinks current, where the device draws the energy back from the output, such as during soft-start from above target output voltage level or soft-stop. Runaway overcurrent (OCR) can occur when the output is short to ground.

Step 4: SS1 Setting

The SS1 pin sets options to attempt regulation following fault events. The two options for fault response due to UC/OC protection are hiccup and brick-wall/latchoff. With hiccup mode, the regulators shut down immediately after UC/OC/OCR/UV or OV occurs. With the brick-wall and latchoff setting, the current fault protection is set to constant current mode. The device attempts to provide continuous output current of 4.2A (which is a peak current limit) in current-sourcing event, while in a current-sinking event it attempts to continuously sink current of 4.2A. The SS1 pin also selects the soft-start time of the dual-phase output and the soft-stop feature enable/disable.

For our dual-phase design, we use brick-wall mode for OC behavior with a 4ms soft-start time and a disabled soft-stop feature. Table 2 gives us the required value of R_SS1 for this configuration as follows, R_SS1 = 200kΩ. How Table 2 should be used for this selection is shown in Table 4 in yellow highlighted text.

Step 5: SS2 Setting

SS2 is still needed to set the LX-slew of both phases. Reducing the LX switching transition time has the benefit of improved efficiency; however, the fast slewing of the LX-slew nodes results in relatively high radiated EMI. The SS2 pin can set the LX-slew rate of both regulators to be either the maximum (5V/ns) or minimum value (0.25V/ns).

For our dual-phase design, we use a minimum value of LX-slew rate to ensure better EMI performance. Table 2 gives us the required value of R_SS2 for this configuration as follows: R_SS2 = 15kΩ. How Table 2 should be used for this selection is shown Table 5 by yellow highlighted text.

Step 6: V_OUT Setting

The target output voltage is achieved by the sum of the coarse and fine voltages. The resistor value can be found from cross-referencing the index number to the resistor value on Table 2. For a target output voltage between 0.904V and 3.782V, the index of the coarse and fine resistors can be calculated as follows.

Coarse V_OUT Setting

For our dual-phase design of output equal to 1.1V, the coarse index can be calculated as follows:

The coarse index of 3 corresponds to R_COARSE1 = 75kΩ and R_COARSE2 = 75kΩ, which corresponds to a COARSEV_OUT of 0.966V.

How Table 2 should be used for this selection is shown in Table 6 by yellow highlighted text.

Fine V_OUT Setting

For our dual-phase design of output equal to 1.1V, the fine index can be calculated as follows:

The fine index of 7 corresponds to R_FINE1 = 24.3kΩ and R_FINE2 = 24.3kΩ, which corresponds to a FINEV_OUT of 0.135V.

How Table 2 should be used for this selection is shown in Table 6 by yellow highlighted text.

The total value of V_OUT can be calculated as follows:

V_OUT can also be calculated as:

Step 7: Duty-Cycle Calculation

The maximum input and output voltages V_INMAX and V_INMIN must accommodate the worst-case conditions accounting for the input voltage variations. Lower input voltages result in better efficiency with a maximum duty cycle of 93%. The maximum V_OUT possible is 0.93 x V_IN.

For our dual-phase design, the maximum and minimum duty cycles can be calculated as follows:

Step 8: Input Capacitor Calculation

The input capacitor must meet the ripple current requirement, I_RMS imposed by the switching currents. The I_RMS requirements of the regulator can be determined by the following equation:

The worst-case RMS current requirement occurs can be calculated as follows:

Solving above and equating to 0 to achieve the worst-case current:

Thus, worst-case RMS current occurs at duty cycle value of 0.5. At this point, the above equation simplifies to I_RMS = 0.5 x I_OUT.

The minimum input capacitor required per phase can be calculated by the following equation:

where average input current per phase can be written as:

For our design of 3A per phase, the average input current per phase is:

The minimum input capacitor required per phase for our design with an input capacitor ripple allowance of 70mV can now be calculated as:

For our design, we selected an input capacitor of 10µF, 25V per phase.

Step 9: Per-Phase Inductor Calculation

The MAX17509 is optimally designed to work with 30% peak-to-peak ripple current to average load current ratio (LIR = 0.3). The switching frequency, input voltage, output voltage, and selected LIR determine the inductor value as follows:

For the selected inductance value, the actual peak-to-peak inductor ripple current can be calculated as follows:

The inductor specification must be large enough not to saturate at the peak inductor current I_PK, or at least in a range where the inductance does not degrade significantly. The maximum per phase peak inductor current I_PK is equal to the maximum load current in addition to half of the peak-to-peak ripple current. I_PK can be calculated as follows:

The runaway peak current limit (5.6A) can be used directly for the inductor saturation current specification of a conservative system design. For our design, we selected Würth Elektronik SMD power inductor 78438356012 of 1.2μH (5.6A saturation current) for each phase.

Step 10: Dual-Phase Total Output Capacitor Calculation

For a dual phase operation, the OUT1 and OUT2 pins should be connected to make a single output. The output capacitor selection requires careful evaluation of several different design requirements: DC voltage rating, stability, transient response, and output ripple voltage. With ceramic capacitors, the ripple voltage due to capacitance dominates the output ripple voltage. Therefore, the minimum total capacitance needed with ceramic output capacitors can be calculated as follows:

For a 3% ripple allowance the minimum C_OUT is:

The load transient response depends on the overall output impedance over frequency, and the overall amplitude and slew rate of the load step. In applications with large, fast load transients (load step > 80% of full load and slew rate > 10A/μs), the output capacitor’s high-frequency response needs to be considered (ESL and ESR needs to be limited). To prevent the output voltage from spiking too low under a load-transient event, the ESR is limited by the following equation:

where V_RIPPLESTEP is the allowed voltage drop during load current transient, and I_OUTSTEP is the maximum load current step. With 5% allowed sag for a load step of 3A, the maximum allowed ESR can be calculated as:

The capacitance value dominates the mid frequency output impedance and continues to dominate the load transient response if the load transient’s slew rate is fewer than two switching cycles. Under these conditions, the sag and soar voltages depend on the output capacitance, inductance value, and delays in the transient response. Low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the output filter capacitors by a sudden load step, especially with low differential voltages across the inductor.

For the selected V_SAG the required output capacitance value can be calculated as follows:

where:

The allowed sag value selected for this design is 5% of the output voltage, V_OUT. The value for C_{OUT_SAG} can now be calculated as follows:

The allowed soar value selected for this design is 8% of the output voltage, V_OUT. The amount of overshoot output voltage (C_{OUT_SOAR}) that comes in to effect after load removal (due to stored inductor energy) can be calculated as:

To consider capacitor tolerances, DC bias characteristics, and to keep soar and sag within the required specification for varying load steps, in our dual-phase design we selected 4 x 100μF (25V) as total output capacitance.

Step 11: Enable Pins Calculations

For a dual-phase design, we need to connect the individual enable pins of two phases (EN1 and EN2) together. EN1 dictates the settings on EN2 too. The design has SW1 to enable both phases together.

To set the voltage at which the device turns on from V_IN, we connect a resistive voltage-divider from the IN pin to GND with the center node of the divider connected to the EN1 pin. See Figure 4.

With a selected value of R_U = 10kΩ, the required value of R_B can be calculated as:

where V_INU = required input voltage at which we require the device to turn on. In our case, we selected V_INU = 4.05V, so:

In our design, we selected R_B = 4.53kΩ.