Hardware Requirements for Lowest Power Consumption in Power-Down Mode for the MAXQ1065

要約

This application note discusses the hardware requirements of the MAXQ1065 Cryptographic Controller for ultra-low power consumption in power-down mode.

Introduction

Setting the PWDN pin of the MAXQ1065 Cryptographic Controller device to GND puts it into the power-down mode. The basic setup shown in the MAXQ1065 data sheet however does not achieve the lowest possible power consumption in power-down mode. To achieve this, there are some specific hardware requirements. This application note discusses the hardware requirements for the MAXQ1065 to put it into the ultra-low power consumption power-down mode. The application note first shows the block diagram and then lists the extra components needed for this specific mode.

MAXQ1065 Ultra-Low Power Block Diagram

Figure 1 shows the block diagram that can be used to achieve the lowest possible power consumption using the MAXQ1065 power-down mode. At both 1.8V/3.3V VDD this setup reduces the current consumption by approximately 75%. Four pullup and four pulldown resistors are all that is needed to get the MAXQ1065 into this ultra-low power consumption power-down mode.

MAXQ1065 hardware setup for ultra-low power operation

Figure 1. MAXQ1065 hardware setup for ultra-low power operation.

MAXQ1065 Ultra-Low Power Component List

Table 1 lists the details of the components shown in Figure 1.

Table 1. MAXQ1065 Ultra-Low Power
MAXQ1065 Pin Connection Resistor Value
RDY Pullup 10k, 1/10W, 1%
RESET_OUT Pullup (see Note) 10k, 1/10W, 1%
WDI Pullup 10k, 1/10W, 1%
TAMPER_IN Pullup 10k, 1/10W, 1%
SPIS_SCK Pulldown 10Meg, 1/10W, 1%
SPIS_MISO Pulldown 10Meg, 1/10W, 1%
SPIS_MOSI Pulldown 10Meg, 1/10W, 1%
SPIS_SS Pulldown 10Meg, 1/10W, 1%
Note: If the RESET_OUT is used for the pin's intended functionality, it needs to be set to the inverse of the connected microcontroller reset pin active state otherwise a pullup is needed.

Summary

This application note has covered the additional hardware needed to put the MAXQ1065 Cryptographic Controller into its ultra-low power consumption power-down mode. For more details on the regular operation of the MAXQ1065 power-down mode, refer to the MAXQ1065 device data sheet.