DS3134 Application Note: PCI Bus Utilization

Overview
The DS3134 accesses the PCI bus to obtain and store HDLC packets as they are sent and received. This application note details how to calculate how much of the available bus bandwidth will be required by the DS3134 to operate properly. Hopefully, with the information provided in the application note, the user can modify the numbers to fit their particular application. Refer to Table 1 to reference the variables used in this article.

Table 1. Definition Of Variables

Type 1: Burst Read by the DMA from the Host RAM
The total number of bus cycles required when the DMA burst reads from the host RAM is [3+R+D]. This equation was derived from Figure 9.1B of the DS3134 data sheet and as shown below.

Type 4: Read by the Host to the DS3134
The total number of bus cycles required when the Host reads from the DS3134 is 7. Note: For Type 3 and 4, the 7-cycle is inherent to Chateau and cannot be changed.

Number Of Bus Cycles Needed Per Packet
In order to calculate bus utilization, the number of bus cycles required must be known. To obtain this number, several assumptions have been made and are listed below. Figure 1 shows the standard sequence that the Host and DMA will follow for each packet received or transmitted. From Figure 1 we can create a formula to calculate the average number of bus cycles required per packet, which is the variable C.

Receive Side
Cr = [(3 + R + 24) / 12] + [(P / 4) + (2 + R)X] + [2 + R + 3] + [(2 + R + 6) / 6] + [4(7 / B)]

Transmit Side
Ct = [(3 + R + 12) / 12] + [2 + R + 1] + [3 + R + 4] + [(P / 4) + (3 + R)X] + [(2 + R + 6) / 6] + [4(7 / B)]

Total Formula
C = 21.16 + 3.5R + 0.5P + 56 / B + (5 + 2R)X

Assumptions Made to Calculate the Number of Bus Cycles Required Per Packet

• All packets are 64 bytes (seen as worse case).
• The FCS of the HDLC packet is not transferred to or from the PCI bus.
• On the receive side, only large buffers are used (small buffers are disabled).
• The receive DMA will burst read the free queue and burst write to the done queue.
• The transmit DMA will burst read the pending queue and burst write the done queue.
• All packets fit within a single buffer (i.e., only one descriptor); reasonable since packets are 64 bytes.
• All physical layer links are filled with packets, no idle codes sent or received.
• Interrupt routines and overhead (like accesses to the local bus) are not considered.

Notes:

1. 12 descriptors x 2 dwords= 24
2. Packet in bytes, 4 bytes/data cycle
3. 6 descriptors x 1 dword = 6

Notes:

1. 12 descriptors x 1 dword = 12.

Following are examples of three cases of bus utilization. In each case, it was assumed that all the incoming and outgoing packets were 64 bytes long (P = 64) and that the host would update and read the queues used by the DMA on the DS3134 on average, every eight packets (B = 8). In each case there are two scenarios. In scenario A, the host RAM is tightly coupled and on average only adds one bus cycle for each access. In scenario B, the host RAM is not tightly coupled and on average adds seven bus cycles for each access. These three examples can be modified to fit the exact application.

Table 2. Description of Examples

NOTES:
Packets per second: (speed of HDLC channel) x (1 byte/8 bits) / (bytes per packet)
Example, Case 1: 64000bps x (1/8) / 64 bytes = 125

Case 1

1. There are 1024 blocks in the Chateau internal FIFO, each block is 4 dwords (16 bytes). With 256 channels loaded, each channel can only be assigned to 1024 / 256 = four blocks (4 x 16 = 64 bytes / channel).
2. Since each FIFO block is 64 bytes, a 64-byte packet in the FIFO can fill or empty in two bus accesses. For worst-case assumptions, we use three in this example.

1. There are 64 channels in Case 2, and, therefore, the block size in the FIFO can be 1024 / 64 = 16 blocks (16 x 16 = 256 bytes/channel).
2. Each FIFO block size is 256 bytes; therefore, a 64-byte packet in the FIFO can fill or empty in one bus access.

1. There are two channels in Case 3, and, therefore, the block size in the FIFO can be 1024 / 2 = 512 blocks (512 x 16 = 8192 bytes/channel).
2. Each FIFO block size is 8192 bytes; therefore, a 64-byte packet in the FIFO can be fill or empty in one bus access.