-
AD9559 Schematic (Rev. A)2/21/2014PDF292 K
製品概要
製品概要
The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates two completely independent output clocks that are synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.For convenience, detailed information from the AD9559 data sheet has been included here. Use this user guide in conjunction with the AD9559 data sheet and software documenta¬tion available at www.analog.com.
- Simple power connection using 6 V wall adapter and on-board LDO voltage regulators
- LDOs are easily bypassed for power measurements
- 4 ac-coupled differential output SMA connectors (which can be reconfigured for up to 8 single-ended outputs.
- 4 inputs SMA connectors that accept either single-ended or differential signals
- USB connection to PC
- Microsoft Windows-based evaluation software with simple graphical user interface and support for both 64-bit and 32-bit operating systems.
- Easy access to digital I/O and diagnostic signals via I/O header
- Status LEDs for diagnostic signals
関連資料
-
AD9559 Bill of Materials2/21/2014XLSX26 K
購入
表示されている価格は、1個あたりの価格です。
価格は1個当たりの米ドルで、米国内における販売価格（FOB）で表示されておりますので、予算のためにのみご使用いただけます。 また、その価格は変更されることがあります。米国以外のお客様への価格は、輸送費、各国の税金、手数料、為替レートにより決定されます。価格・納期等の詳細情報については、弊社正規販売代理店または担当営業にお問い合わせください。なお、 評価用ボードおよび評価用キットの表示価格は1個構成としての価格です。