LTC4218 12V/100A Hot Swap Design for Server Farms

Cultivate reliability on the farm with a properly designed Hot Swap circuit.


As data centers servicing the cloud grow in speed and capacity, backplane supplies are called on to deliver currents that push the performance boundaries of Hot Swap components. Hot Swap solutions allow boards to be inserted and removed from a live backplane without disturbing the power distributed to other boards. A typical Hot Swap solution uses a series MOSFET to manage the flow of power between the backplane and the board—preventing glitches and faults from disrupting power to the rest of the system.

The challenges of designing robust Hot Swap solutions multiply with increasing current demands. With load currents at 100A, simply determining power dissipation requirements is no longer sufficient. Designers must pay careful attention to the MOSFET safe operating area (SOA) and understand Kelvin current sensing techniques for multiple sense resistors. This article shows how to address these issues using the example of a 12V/100A solution based on the LTC4218 Hot Swap controller.

12V/100A Hot Swap Design

Figure 1 shows the LTC4218 Hot Swap controller managing power to a board that contains up to 1000μF of bypass capacitance, draws up to 100A of load current and is hot plugged into a 12V backplane supply.

Figure 1. 12V/100A Hot Swap solution

Figure 1. LTC4218 12V/100A Hot Swap Solution

Supporting the 100A load current without excessive power dissipation in the MOSFETs M1 and M2 requires that the PG (power good) signal disable the load until the output is fully powered. Typically, this is implemented by controlling the RESET signal of downstream circuitry with the Hot Swap controller’s PG signal. In the circuit of Figure 1, if the effective load resistance is greater than 10Ω during start-up (while PG is low), the output powers up normally. If the output resistance is low during start-up (such as might occur during an output short-circuit fault), the LTC4218 detects this condition and turns off the series MOSFET.

During start-up, the circuit’s current limit threshold is reduced by pulling the LTC4218’s ISET pin low through R4 until the PG signal transitions high. R4’s 3kΩ resistance lowers the current limit threshold to roughly 13% of the normal operating current limit. Any fault conditions that sink extra current beyond that level during start-up cause the TIMER to activate and shut off the MOSFET. (The relatively small components M3, M4, R6, R7, and C4 work together to effectively connect R4’s 3k resistance between ISET and ground when the PG pin is pulling low.)

The output ramp rate during start-up is set by the LTC4218’s 24μA pull-up current into C1 and the gates of MOSFETs M1 and M2. The result is an output ramp rate of 2V/ms. Because the load circuitry is disabled by the PG signal, the current at start-up is dedicated to charging the capacitance downstream of the Hot Swap circuit, represented by C6 in Figure 1. Ramping the 1000μF of capacitance at 2V/ms requires 1000μF • (2V/ms)=2A of current. This is far below the start-up current limit threshold set by R4 at 16A or 13% of the normal operating current limit. This allows plenty of margin for inaccuracies in the current sensing. Exceeding this current limit threshold for even a short time during start-up indicates a fault condition at the output, and the LTC4218 responds by turning off MOSFETs M1 and M2.

MOSFET Safe Operating Area

In this application, the entire SOA can be satisfied by M1 or M2 alone. It is unwise to assume that current and SOA share equally among MOSFETs during start-up or output overload faults that cause significant drain to source voltages across the MOSFETs. Either MOSFET should be able to support the entire SOA of the application.

On the other hand, when the MOSFET is fully enhanced during normal operation, its behavior is similar to a resistor and it is safe to assume that current shares more equally. In this application, two MOSFETs are used to reduce the power dissipation during normal operation, not to satisfy transient safe operation area requirements. At 100A, the power dissipated by a single 1mΩ MOSFET is I2R = (100A)2 • 1mΩ = 10W. If the current shares equally at 50A, the power in each MOSFET is a more reasonable I2R = (50A)2 • 1mΩ = 2.5W.

Proper Kelvin Sensing with Multiple Sense Resistors

At these current levels, properly monitoring the voltage across the sense resistance can be challenging. With the LTC4218’s 15mV current sense threshold, a 100A current limit requires less than 0.15mΩ of sense resistance, usually achieved using parallel resistors in a Kelvin sensing scheme.

When a single sense resistor is used in Hot Swap (or other current sense) applications, it is common practice to use separate low current Kelvin traces between the sense pins of the IC and the sense resistor. An example layout of Kelvin connections to a current sense resistor is shown in Figure 2. The low current Kelvin sense paths directly between the sense resistor and the LTC4218 SENSE+ and SENSE pins eliminate errors due to the voltage drops that occur when high currents pass through the resistive PCB copper.

Figure 2. Kelvin sensing with single sense resistor

Figure 2. Kelvin sensing with single sense resistor

In this 100A application, though, it is necessary to implement the sense resistance with multiple parallel sense resistors. Eight 1mΩ resistors in parallel is a reasonable choice, as it results in a typical current limit of 8 • (15mV/1mΩ) = 120A, providing a comfortable margin above the 100A delivered to the load.

Nevertheless, multiplying the number of sense resistors multiplies the layout challenges; the straightforward layout shown for a single resistor in Figure 2 no longer suffices. Current rarely shares equally among the sense resistors—it is not unusual to see a 50% difference in current between several low value sense resistors in high current applications. The resistors placed more closely to MOSFETs M1 and M2 conduct a greater proportion of the load current than the sense resistors placed farther away, due to the finite resistance of the PC board copper planes showing up in series with the sense resistors. If possible, the preferred layout is to place an equal number of sense resistors on the top and the bottom of the PC board. This minimizes the parasitic voltage drops caused by the lateral current flow through the copper planes required to reach the farthest sense resistor.

Even with an optimal PC board layout, it is necessary to use a resistor network to average the voltages sensed across the individual 1mΩ resistors. In this 12V/100A application, the SENSE+ and SENSE pins of the LTC4218 are joined to the eight 1mΩ sense resistors with an array of 1Ω resistors as shown in Figure 1. The resulting voltage between the SENSE+ and SENSE pins is the average of all of the voltages across the 1mΩ sense resistors, effectively Kelvin sensing the eight 1mΩ resistors. An example layout is shown in Figure 3.

Figure 3. Kelvin sensing layout for eight parallel resistors uses top and bottom of board

Figure 3. Kelvin sensing layout for eight parallel resistors uses top and bottom of board

Lab Results

Of course, calculations and circuit simulations are no substitute for benchtop testing, especially when working with high current Hot Swap solutions. Figure 4 shows an oscilloscope waveform of this design starting up into a 100Ω resistor followed by a 100A load step after the ENABLE/RESET signal transitions high. Note that the ENABLE/RESET in this setup drives the 4V ON signal of an electronic load box rather than the 12V level from M5 and R10 shown in Figure 1.

Figure 4. Normal start-up

Figure 4. Normal start-up

The waveform in Figure 4 is typical of proper operation when no faults are present. The 12V input supply ramps up first. Then, the LTC4218 charges the 1000μF output capacitor at 2V/ms. Finally, the 100A load turns on when the ENABLE/RESET output transitions high, signaling that the MOSFETs M1 and M2 are fully enhanced.

Figure 5 shows the LTC4218 turning off MOSFETs M1 and M2 when a short circuit occurs on the output. 100ms after the input voltage rises, the circuit begins to charge the output node. The LTC4218 limits the charging current to the 16A start-up current limit threshold and quickly detects the short-circuit. This solution responds properly and shuts off power to the load to avoid any disruption (and damage) to other components in the system.

Figure 5. Start-up into a short circuit

Figure 5. Start-up into a short circuit


Over the years, the designers of Hot Swap solutions have had to continually address fresh challenges posed by ever increasing supply currents. Some issues are not new, such as the power dissipation requirements that result from high current, but today’s current levels have pushed some new design issues to the fore, such as MOSFET safe operating area, and the Kelvin sensing techniques for multiple sense resistors. The 12V/100A LTC4218 Hot Swap controller solution shown here specifically addresses these design points.



Dan Eddleman

Dan Eddleman is an analog engineer with over 15 years of experience at Linear Technology as an IC designer, the Singapore IC Design Center Manager, and an applications engineer.

He began his career at Linear Technology by designing the LTC2923 and LTC2925 Power Supply Tracking Controllers, the LTC4355 High Voltage Dual Ideal Diode-OR, and the LTC1546 Multiprotocol Transceiver. He was also a member of the team that designed the world’s first Power over Ethernet (PoE) Controller, the LTC4255. He holds two patents related to these products.

He subsequently moved to Singapore to manage Linear Technology’s Singapore IC Design Center, overseeing a team of engineers that designed products including Hot Swap controllers, overvoltage protection controllers, DC/DC switched-mode power supply controllers, power monitors, and supercapacitor chargers.

Upon returning to the Milpitas headquarters as an applications engineer, Dan created the Linduino, an Arduino-compatible hardware platform for demonstrating Linear Technology’s I2C- and SPI-based products. The Linduino provides a convenient means to distribute C firmware to customers, while also providing a simple rapid prototyping platform for Linear Technology’s customers.

Additionally, in his role as an applications engineer, he conceived of the LTC2644/LTC2645 PWM to VOUT DACs, and developed the XOR-based address translator circuit used in the LTC4316/LTC4317/LTC4318 I2C/SMBUS Address Translators. He has applied for patents related to both of these products. Dan has also developed multiple reference designs that satisfy the onerous MIL-STD-1275 28V military vehicle specification.

Dan continues to study Safe Operating Area of MOSFETs, and has created software tools and conducts training sessions within Linear Technology related to SOA. His SOAtherm model distributed with LTspice allows customers to simulate MOSFET SOA within their Hot Swap circuit simulations using thermal models that incorporate Spirito runaway.

He received an M.S. in Electrical Engineering from Stanford University and B.S. degrees in Electrical Engineering and Computer Engineering from the University of California, Davis.