Hardware Description
The MAX17536 high-efficiency, high-voltage, synchronous step-down DC-DC converter with integrated high-side MOSFET operates over a 4.5V to 60V input. The converter delivers up to 4A and generates output voltages from 0.9V up to 0.9 × VIN.
The MAX17536 uses peak current-mode control. The device may be operated in the pulse-width modulation (PWM), pulse-frequency modulation (PFM), and discontinuous-conduction mode (DCM) control schemes.
Mode Selection
The logic state of the MODE/SYNC pin is latched when VCC and EN/UVLO voltages exceed the respective UVLO rising thresholds and all internal voltages are ready to allow LX switching. If the MODE/SYNC pin is open at power-up, the device operates in PFM mode at light loads. If the MODE/SYNC pin is grounded at power-up, the device operates in constant-frequency PWM mode at all loads. Finally, if the MODE/SYNC pin is connected to VCC at power-up, the device operates in constant-frequency DCM mode at light loads. State changes on the MODE/SYNC pin are ignored during normal operation.
In PWM mode, the inductor current is allowed to go negative. PWM operation provides constant frequency operation at all loads, and is useful in applications sensitive to switching frequency. However, the PWM mode of operation gives lower efficiency at light loads compared to PFM and DCM modes of operation.
PFM mode of operation disables negative inductor current and additionally skips pulses at light loads for high efficiency. In PFM mode, the inductor current is forced to a fixed peak of 2A every clock cycle until the output rises to 102.3% of the nominal voltage. Once the output reaches 102.3% of the nominal voltage, both the high-side and low-side FETs are turned off and the device enters hibernate operation until the load discharges the output to 101.1% of the nominal voltage. Most of the internal blocks are turned off in hibernate operation to save quiescent current. After the output falls below 101.1% of the nominal voltage, the device comes out of hibernation, turns on all internal blocks, and again commences the process of delivering pulses of energy to the output until it reaches 102.3% of the nominal output voltage. The advantage of the PFM mode is higher efficiency at light loads because of lower quiescent current drawn from the supply. The disadvantage is that the output-voltage ripple is higher compared to PWM or DCM modes of operation and switching frequency is not constant at light loads.
DCM mode of operation features constant-frequency operation down to lighter loads than PFM mode, by not skipping pulses but only disabling negative inductor current at light loads. DCM operation offers efficiency performance that lies between PWM and PFM modes.
Table 1 shows Reference Design jumper (JU1) settings that can be used to configure the desired mode of operation.
Table 1. MODE Description (JU1)
| Shunt Position |
EN/UVLO Pin |
MAX17536 Mode |
| 1-2* |
Connected to SGND |
PWM Mode of Operation |
| Not Installed |
Unconnected |
PWM Mode of Operation |
| 2-3 |
Connected to VCC |
CDM Mode of Operation |
*Default position.
Linear Regulator (VCC and EXTVCC)
The device has two internal low-dropout (LDO) regulators which power VCC. One LDO is powered from VIN (IN LDO) and the other LDO is powered from EXTVCC (EXTVCC LDO). Only one of the two LDOs is in operation at any given time, depending on the voltage levels present at EXTVCC. If the EXTVCC voltage is greater than 4.7V (typ), VCC is powered from EXTVCC. If EXTVCC is lower than 4.7V (typ), VCC is powered from VIN. Powering VCC from EXTVCC increases efficiency at higher input voltages. EXTVCC voltage should not exceed 24V.
Loop Compensation
The MAX17536 is internally loop compensated. However, if the switching frequency is less than 450kHz, connect a 0402 capacitor (C10) between the CF pin and the FB pin to keep the compensation loop stable.
Input Undervoltage-Lockout Level Setting (EN/UVLO)
The MAX17536 offers an adjustable input undervoltage-lockout level. Set the voltage level with a resistive voltage-divider connected from VIN to SGND. Connect the center node of the divider to EN/UVLO.
Choose R1 to be 3.32M and then calculate R2 as follows:
where VINU is the voltage required to turn on the device. The VINU in this design is 14.5V.
For normal operation, a shunt should be installed across pins 1-2 on JU2. To disable the output, install a shunt across pins 2-3 on JU2 and pull the EN/UVLO pin to GND. See Table 2 for JU2 settings.
Table 2. Regulator Enable (EN/UVLO) Description (JU2)
| Shunt Position |
EN/UVLO Pin |
MAX17536 Mode |
| 1-2* |
Connected to VIN |
Enabled |
| Not Installed |
Connected to the Center Node of Resister-Divider R1 & R2 |
Enabled, UVLO Level Set through the R1 and R2 Resistors |
| 2-3 |
Connected to SGND |
Disabled |
*Default position.
