MAXREFDES1202

The MAXREFDES1202 is a dual-phase, buck converter reference design developed using the MAX17558, MAX15019A, and MAX17552. This reference design is rated to operate over a wide input voltage range from 15V to 55V. The design can deliver an output power of 360W at 12V.

Main features include the following:

• Very High Efficiency > 95% at Full Load
• Very Low Line Regulation < 0.1% and Very Low Load Regulation < 0.25%
• Inductor DCR Current Sensing
• Output-Voltage Ripple < 0.5% at V_IN (nom)
• Overshoot < 3% for 50% Step Load

A single-output, dual-phase buck converter is demonstrated for a 15V to 55V input voltage range application. The output is 12V, delivering 30A of current at full load.

The MAX17558 is used for controlling the converter. This IC is a dual-output, synchronous step-down controller using a constant-frequency, peak-current-mode architecture. It has wide input supply range of 4.5V to 60V. The device also provides the ability to run two controllers 180° out of phase to reduce power loss and noise due to the input-capacitor ESR.

The gate pulses from the MAX17558 are input to the MAX15019A gate driver, which is used for driving the MOSFETs. The MAX15019A is a high-frequency, 125V half-bridge, n-channel MOSFET driver that drives high and low-side MOSFETs. This IC supports supply voltages from 8V to 12.6V V_DD, thus making it suitable for driving MOSFETs with higher gate threshold voltage.

The power supply for the gate driver is derived from the MAX17552 low-cost, high-voltage buck controller IC.

Table 1 shows an overview of the design specification.

This document describes the hardware shown in Figure 1. It provides a detailed, systematic technical guide for designing a dual-phase buck converter using the MAX17558 currentmode controller. This power supply has been built and tested, details of which follow later in this document.

Required Equipment

• DC Power Supply
• DC Electronic Load
• Multimeter
• Oscilloscope

Procedure

This reference design is fully assembled and tested. Follow these steps to verify board operation:

1. Connect a 60V DC power supply to the input.
2. Keep the input voltage at 48V and turn on.
3. Observe the output voltage using a multimeter. It should show 12V.
4. Connect a DC electronic load at the output and load in steps up to 30A. Observe the output-voltage regulation and output ripple.

Figure 2 shows the electrical block diagram of a dualphase buck converter. The two phases share a common input and load. Current delivered to the load is shared equally by the inductors and switches. Each phase is operated with 180° phase difference between the PWM gate signals for improved ripple performance.

Compared to single-phase buck regulators, a dual-phase buck converter offers several advantages as follows:

1. Load Sharing
2. Input Ripple Reduction
3. Output Ripple Reduction

As seen in Figure 2, the two phases are operated at a 180° phase shift. G₁ and G₂ are the gate signals applied to the top switches of their respective phases. I_L1 and I_L2 are the inductor currents, I_QT1 and I_QT2 are the top switch currents, and I_CO is the output capacitor current.

Assuming that the current drawn from the input supply is DC, the AC of the switch currents I_QT1 and I_QT2 is supplied by the input capacitor. The phase shift of the two switch currents effectively reduces the peak of the input current by half, while the frequency is doubled.

Similarly, the inductor currents I_L1 and I_L2 supply the load. A 180° phase shift between the two phases causes a reduced ripple current (I_CO) in the output capacitor.

Inductor

The required inductance per phase is calculated based on the inductor ripple current ratio (LIR). This is defined as the ratio of the peak-to-peak inductor current (ΔI_L) to the average current (I_O). For a switching frequency:

and operating at a minimum duty cycle:

and

the inductance required per phase is calculated by applying volt-second balance on the inductor voltage as follows:

With LIR at 0.4 and the load current at 15A (per phase current), the value of inductance is calculated. Based on the calculated specifications for the inductors, the Coilcraft® VER2923-153KL was selected.

The losses in the inductor have two components: copper loss and core loss. The core loss is obtained from the manufacturer website. The copper loss is calculated as follows:

Inductor copper loss = I_L—RMS² × R_CS

where:

R_CS is the DC resistance (DCR) of the inductor. DCR is used for current sensing in this reference design.

R_CS = 2.6mΩ

Table 2 gives a summary of the calculated values for power loss in each inductor.

Current Sensing

An inductor DCR is used for current sensing in this design. This effectively reduces the losses associated with two current shunt resistors, leading to improved efficiency. The voltage across the inductor is conditioned to obtain the current signal.

Figure 3 shows the DCR current-sensing circuit. An RC low-pass filter is connected across the inductor, which has a DC resistance of R_CS.

The equations relating the current through the inductor and voltage developed across the inductor can be written in the Laplace domain as follows:

having:

The sensed voltage (V_CS) is a simple gain multiplied by the inductor current (I_L), V_CS = R_CSI_L(s), and the values are R_C = 17.4kΩ and C_C = 330nF.

Table 3 gives the values of current-sense signal (V_CS) for the full load current at a nominal input voltage of 48V.

MOSFETs

The current and voltage waveforms in the synchronous switches during on and off period are shown in Figure 4a for one phase. The on-state losses are due to a resistive drop in the MOSFETs.

The RMS current and the conduction power loss (P_T—CONDN) in the top device of a phase are given by the following equations:

P_T—CONDN = I_{QT1 RMS}² x R_RDS—ON

Figure 4b shows the turn-on and turn-off transients in the MOSFET. I_D is the drain current and V_DS is the drain-tosource voltage of the MOSFET. The switching loss (P_T-SW) during turn-on and turn-off transients and the gate charging loss (P_T-GATE) are calculated as follows:

P_T—SW = f _SWV_INI₁∆t

P_{T—GATE = QGVDRIVEfSW}

The total power losses (P_T) in the top MOSFET per phase are calculated as follows:

P_T = P_T—CONDN + P_T—SW + P_T—GATE

Refer to the BOM in the Design Resources tab for the components chosen.

The RMS current I_QB1-RMS and on-state conduction losses (P_B-CONDN) in the bottom device are given by the following equations:

P_B—CONDN = I_QB1—RMS² x R_RDS—ON

During dead times (when DH is falling and DL is rising or when DL is falling and DH is rising), the body diode of the lower MOSFET conducts to maintain current through the inductor. This can be termed as “dead-time loss” (P_B-DT). Also, when the top MOSFET is turning on, the body diode of the lower MOSFET recovers to the blocking state, leading to reverse-recovery losses (P_RR) in the device.

P_RR = Q_RRV_INf_SW

Table 5 shows the summary of losses in the bottom MOSFET.

Output Capacitor

Figure 5 shows the current in the two inductors and in the output capacitor when operating in full load at a nominal input voltage. The capacitor sees the ripple current at twice the switching frequency of the inductor current.

The ratio of the peak-to-peak capacitor ripple current to the inductor ripple current is around 0.75 at duty cycle of 0.25. The RMS current through the output capacitor is calculated as follows:

The output capacitance (C_OUT) depends on the desired steady-state voltage ripple and voltage overshoot specification. The steady-state ripple (ΔV_{O_SS}) has 2 components: one due to drop in actual capacitance (ΔV_{O_Q}) and another due to drop in ESR of the capacitor (ΔV_{O_ESR}).

ΔV_{O_SS} = ΔV_{O_ESR} + ΔV_{O_Q}

For ceramic capacitors, ΔV_{O_Q} predominates. For electrolytic capacitors, the ΔV_{O_ESR} component predominates.

For a steady-state ripple of ΔV_{O_SS}, the desired output capacitance is calculated from the following equations:

For achieving good transient performance, the required output capacitance is calculated as:

where ΔI_O is the total load change, f_C is the unity gain bandwidth (or crossover frequency), and ΔV_{O_OS} is the transient overshoot specification.

A combination of electrolytic and ceramic capacitors has been used for optimal performance in this design. Table 6 shows the summary of current and loss in the output capacitor.

Input Capacitor

The input filter capacitor reduces the peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit’s switching.

Figure 6 illustrates the current flowing through the switch and input capacitor during rated operating voltage and current. For a DC current drawn from the input (I_IN = DI_O), the RMS current flowing through the input capacitor for a single-phase buck converter is given as:

The RMS of the current in input capacitor for a dual-phase buck converter under nominal operating conditions (D < 0.5) is given as:

Compensation

Figure 7 shows the control block diagram of a dual-phase buck converter. The output-voltage error amplifier of both phases operates in parallel to derive a single control signal (V_C). Here, G_CS is the current-sense amplifier gain, G_M is the internal transconductance error amplifier gain, and G_FB is the output-voltage feedback divider gain (0.8/output voltage).

The plant transfer function consists of the pole f_P1 formed by the load and output capacitor:

An additional zero (f_Z1) is introduced by the output capacitor ESR:

The voltage error amplifier transfer function introduces one zero and two poles.

The crossover frequency is kept at 1/10th of the switching frequency f_SW, and R_Z is calculated from the following:

C_Z is calculated by placing the compensator zero near the system pole f_P1:

C_P is calculated by placing the compensator pole near f_Z1, or half of the switching frequency, whichever is the minimum: