MAXREFDES1175

Power over Ethernet (PoE) is a technology that allows network cables to deliver power to a powered device (PD) through power-sourcing equipment (PSE) or midspan, and has many advantages over traditional methods of delivering power. PoE allows power and data to be combined, removing the need for altering the AC mains infrastructure and can be installed by non-electricians. PoE is an intelligent system designed with protection at the forefront, preventing overload, underpowering, and installation errors, while allowing simple scalability and reliability.

The MAX17690 implements an innovative algorithm to accurately determine the output voltage by sensing the reflected voltage across the primary winding during the flyback time interval. By sampling and regulating this reflected voltage when the secondary current is close to zero, the effects of secondary-side DC losses in the transformer winding, the PCB tracks, and the rectifying diode on output voltage regulation can be minimized. The MAX17690 also compensates for the negative temperature coefficient of the rectifying diode.

Other features include the following:

• IEEE 802.3af/at Compliance
• Thermally Enhanced, 3mm × 3mm, 10-Pin TDFN Package (MAX5969B)
• 30V to 60V Input Voltage Range
• Programmable Switching Frequency from 50kHz to 250kHz
• Programmable Input Enable/UVLO Feature
• Programmable Input Overvoltage Protection
• Adjustable Soft-Start
• 2A/4A Peak Source/Sink Gate Drive Capability
• Hiccup Mode Short-Circuit Protection
• Fast Cycle-by-Cycle Peak Current Limit
• Thermal Shutdown Protection
• Space-Saving, 16-Pin, 3mm × 3mm TQFN Package
• -40°C to +125°C Operating Temperature Range

This reference circuit consists of the MAX5969B PD controller and an isolated no-opto flyback DC-DC converter using the MAX17690 to demonstrate a 5V DC output application. A 1GbE RJ45 magnetic jack is also included as well as two diode bridges for separating data and DC power provided by an endspan or midspan PoE system. The low-resistance, on-chip MOSFETs ensure high efficiency at full load and simplifies layout. The power supply delivers up to 1.4A at 5V. Table 1 is an overview of the design specification.

This document describes the hardware shown in Figure 1. It provides a detailed technical guide to designing a complete interface for a PD to comply with the IEEE 802.3af/at standard in a PoE, class 3 system and an isolated no-opto flyback DC-DC converter using Analog Devices' MAX17690 controller. The power supply has been built and tested.

A PoE system delivers power and data to an end device (PD) typically through an RJ45 cable power from an endspan (PSE) (Figure 2) or a midspan (Figure 3). The power is separated from the data through diode bridges to deliver a typical 48V for efficient power transfer, which is low enough to be considered a safe voltage, removes the need to rewire AC mains, and saves cost.

Although this voltage is safe for humans, it still can damage equipment if not properly delivered. This is where MAX5969B classification is required, ensuring the equipment can handle the power delivery. Before the PSE can enable power to a connected IP camera or other PD, it must perform a signature detection.

Signature Detection

Signature detection uses a lower voltage to detect a characteristic signature of IEEE-compatible PDs (a 24.9kΩ resistance). See Figure 4. Once this signature has been detected, the PSE knows that higher voltages can be safely applied. The PSE applies two voltages on V_IN in the range of 1.4V to 10.1V (1V step minimum) and then records the current measurements at the two applied voltages. The PSE then computes the change in current when each voltage was applied (ΔV/ΔI) to ensure the presence of the 24.9kΩ signature resistor.

Classification

In classification mode, the PSE classifies the PD based on the power consumption required. (The IEEE 802.3af/at standard defines only Class 0 to 4 and Class 5 for any special requirement.)

An external resistor (R_CLS) of 43.7Ω connected from CLS to V_SS sets the classification current. The PSE determines the class of a PD by applying a voltage at the PD input and measuring the current sourced from the PSE. When the PSE applies a voltage between 12.6V and 20V, the MAX5969A/MAX5969B exhibit a current of 26mA to 30mA.

The PSE uses the classification current information to classify the power requirement of the PD (MAX5969B).

The classification current includes the current drawn by R_CLS and the supply current of the MAX5969A/MAX5969B so the total current drawn by the PD is within the IEEE 802.3af/at standard figures. The classification current is turned off whenever the device is in power mode (Figure 5).

Power Mode

The final stage after detection and classification of a newly connected PD is to enable power. The 48V supply from the PSE is connected to the PD through the RJ45 cable. Once enabled, the PSE continues to monitor how much current is being delivered to the PD and cuts power to the cable if the power drawn is not within the correct range. This protects the PSE against overload, underpowering and ensuring that the PSE is disconnected from the cable if the PD is unplugged or faulted. See Figure 6.

The MAX5969B enters power mode when V_IN rises above the undervoltage lockout threshold (V_ON). Note that V_ON/V_OFF = 38.6V/31V for the MAX5969B. When V_IN rises above V_ON, the MAX5969B turns on the internal n-channel isolation MOSFET to connect GND to RTN. The open-drain power-good output (PG) remains low for a minimum of t_DELAY until the power MOSFET fully turns on to keep the downstream DC-DC converter disabled during inrush. The P_GOOD open-drain output is also connected to three small-signal transistors to prevent the DC converters from powering up before the power from the PD is allowable.

Design Considerations for MAX5969B

Place the input capacitor, classification resistor, and transient voltage suppressor as close as possible to the MAX5969A/MAX5969B. Use large SMT component pads for power dissipating devices such as the MAX5969A/MAX5969B and the external diodes. Use short and wide traces for high-power paths.

The MAX5969B enters undervoltage lockout when the input voltage drops below 31V. When the input drops below this value, the isolation MOSFET switches off, disconnecting the 48V from the buck converters. The MAX5969B exits undervoltage lockout when the input exceeds 38.6V, where the isolation MOSFET switches on again, connecting the MAX17690 Flyback Converter.

*V_IN is measured across the MAX5969A/MAX5969B input V_DD to V_SS.

Designing the No-Opto Flyback Converter Using MAX17690

The converter design process can be divided into three parts: the power stage design, the setup of the MAX17690 no-opto flyback controller, and closing the control loop. This document is intended to complement the information contained in the MAX17690 data sheet.

The following design parameters are used throughout this document:

Throughout the design procedure reference is made to the schematic. See the Design Resources section.

Part I: Designing the Power Components

Step 1: Calculate the Minimum Turns Ratio for the Flyback Transformer

The secondary-primary turns ratio, n_SP, and the duty cycle, D, for the flyback converter are related by the flyback DC gain function as follows:

The converter's absolute minimum input voltage is the undervoltage lockout threshold (V_IN falling) which is programmed with a resistor divider for the MAX17690. At this voltage, and at maximum output power, D should be less than or equal to 66% (maximum duty cycle at which the MAX17690 can operate) to ensure reliable operation of the converter. For the current design the undervoltage lockout threshold (V_IN falling) occurs at 29V, so with D set at 66% the absolute minimum turns ratio, n_SP(MIN), for the flyback transformer is calculated:

This transformer turns ratio assumes that there are no DC voltage drops in the primary and/or secondary circuits. In practice a larger transformer turns ratio must be chosen to account for these DC voltage drops. For the current design a transformer turns ratio n_SP = 0.25 was chosen.

Step 2: Estimate the Maximum and Minimum Duty Cycle Under Normal Operating Conditions

Normal input voltage operating conditions are defined as V_IN(MIN) and V_IN(MAX) on page 1. By using the flyback DC gain function again, the duty cycle is estimated as:

n_SP and V_OUT are fixed so clearly D_MAX occurs when V_IN is a minimum, i.e., at V_IN(MIN). For the current design V_IN(MIN) = 30V, so:

The MAX17690 derives the current, ΔI_LP, in the primary magnetizing inductance by measuring the voltage, ΔV_RCS, across the current-sense resistor (R_CS) during the on-time of the primary-side MOSFET, So:

ΔI_LP is a maximum at D_MAX and V_IN(MIN) and a minimum at D_MIN and V_IN(MAX), so:

and

Solving these two equations:

where ΔV_RCS(MIN) and ΔV_RCS(MAX) correspond to the minimum current-limit threshold (20mV) and the maximum current-limit threshold (100mV) of the MAX17690, respectively. So, for V_IN(MIN) = 30V, V_IN(MAX) = 60V, and D_MAX = 0.40, we have:

Step 3: Calculate the Maximum Allowable Switching Frequency

The isolated no-opto flyback topology requires the primary-side MOSFET to constantly maintain switching, otherwise there is no way to sense the reflected secondary-side voltage at the drain of the primary-side MOSFET. The MAX17690 achieves this by having a critical minimum on-time, t_ON(CRIT), for which it drives the MOSFET. At a given switching frequency, t_ON(MIN) corresponds to D_MIN. From the MAX17690 data sheet, the critical minimum on-time t_ON(CRIT) for the NDRV pin is 235ns. We can therefore calculate the maximum allowable switching frequency to ensure that t_ON(CRIT) > t_ON(CRIT) as follows:

Because D_MIN is fixed by ΔV_RCS(MIN), ΔV_RCS(MAX), D_MAX, V_IN(MIN), and V_IN(MAX), then t_ON(MIN) can be chosen arbitrarily larger than t_ON(CRIT) so that f_SW is less than f_SW(MAX). With t_ON(MIN) = 398ns, the switching frequency is:

Note that the MAX17690 should always be operated in the switching frequency range from 50kHz to 250kHz and t_ON(MIN) must be chosen accordingly to ensure that this constraint is met.

Step 4: Calculate Primary Magnetizing Inductance

Maximum input power is given by:

For the DCM flyback converter, all the energy stored in the primary magnetizing inductance, L_P, during the primary-side MOSFET on-time is transferred to the output during the primary-side MOSFET off-time, i.e., the full power transfer occurs during one switching cycle, and since E = P × t:

The maximum input energy must be stored in L_P during the on-time of the primary-side MOSFET, so:

The peak current in L_P, ΔI_LP(MAX), occurs at V_IN(MIN) and t_ON(MAX), so:

and substituting:

combining with the original P × t equation gives:

Finally, rearranging gives an expression for the primary magnetizing inductance, L_P:

Estimating the converter efficiency at 90% and with V_IN(MIN) = 30V, D_MAX = 0.40, V_OUT = 5V, and f_SW = 143.3kHz, then:

This inductance represents the maximum primary inductance, since it sets the current-limit threshold. Choosing a larger inductance sets the current-limit threshold at a lower value and could cause the converter to go into current limit at a value lower that I_OUT, which would be undesirable. Assuming a ±10% tolerance for the primary magnetizing inductance gives:

Step 5: Recalculate D_MAX, D_MIN, and t_ON(MIN) Based on Selected Value for L_P

Rearranging the L_P equation in Step 4 gives an expression for D_MAX as follows:

Referring to Step 2:

and:

Step 6: Calculate the Peak and RMS Currents in the Primary Winding of the Flyback Transformer

The peak primary winding current occurs at V_IN(MIN) and D_MAX according to the following equation:

The RMS primary winding current can be calculated from ΔI_LP(MAX) and D_MAX as follows:

Step 7: Calculate the Peak and RMS Currents in the Secondary Winding of the Flyback Transformer

The peak current in the secondary-side winding of the flyback transformer can be established by considering that the entire energy transferred from the primary-side winding to the secondary-side winding is delivered to the load during one switching period. Again, because E = P × t:

substituting:

and rearranging:

Current flows in the secondary-side winding of the flyback transformer during the time the secondary-side rectifying device is conducting. This conduction time, t_ON(SEC), is calculated using the inductor volt-second equation:

where V = V_OUT, L = L_S, dI = ΔI_LS(MAX), and dt = t_ON(SEC), so:

The maximum duty cycle of the secondary-side rectifying device, D_S(MAX), can now be calculated:

Finally, the RMS secondary winding current can be calculated from ΔI_LS(MAX) and D_S(MAX) as follows:

Step 8: Summarize the Flyback Transformer Specification

All the critical parameters for the flyback transformer have been calculated and are summarized below. Using these parameters, a suitable transformer can be designed.

Step 9: Calculate Design Parameters for Secondary-Side Rectifying Device

Depending on the output voltage and current, a choice can be made for the secondary-side rectifying device. Generally, for output voltages above 12V at low currents (less than 1A) Schottky diodes are used, and for voltages less than 12V synchronous rectification (MOSFET) is used. The current design is a 5V/1.4A output converter, but since this is a non-synchronous design, a procedure for selecting a suitable Schottky diode is outlined.

Figure 7 shows a simplified schematic with the Schottky diode D_FR.

The important parameters to consider for the Schottky diode are peak instantaneous current, RMS current, voltage stress, and power losses. Because D_FR and L_S are in series, they experience the same peak and RMS currents, so:

and:

When D_FR is reversed-biased, V_IN reflected to the secondary-side of the flyback transformer plus V_OUT is applied across the cathode-anode of D_FR, so:

D_FR has both forward conduction losses and reverse bias losses. Allowing for reasonable design margin, the Diodes Incorporated SBRT10U50SP5 was chosen for this design with the following specifications:

The power losses in the D_FR can be approximated as follows:

where:

P_FRWD is the loss due to I_DFR(RMS) flowing through the forward-biased junction of D_FR:

P_REV is the loss due to the reverse-leakage current flowing through the reverse biased junction of D_FR:

Step 10: Calculate Design Parameters for Primary-Side MOSFET

The important parameters to consider for the primary-side MOSFET (Q_P) are peak instantaneous current, RMS current, voltage stress, and power losses. Because Q_P and L_P are in series they experience the same peak and RMS currents, so from Step 6:

Fairchild is a trademark of Fairchild Semiconductor Corporation.

and:

When Q_P turns off, V_OUT reflected to the primary side of the flyback transformer plus V_IN(MAX) is applied across the drain-source of Q_P. In addition, until Q_S starts to conduct, there is no path for the leakage inductance energy to flow through. This causes the drain-source voltage of Q_P to rise even further. The factor of 1.5 in the equation below represents this additional voltage rise; however, this factor can be higher or lower depending on the transformer and PCB leakage inductances:

Allowing for reasonable design margin, the Fairchild® FDMS86252 was chosen for this design with the following specifications:

The power losses in the Q_P can be approximated as follows:

where:

P_CON is the loss due to I_QP(RMS) flowing through the drain-source on resistance of Q_P:

P_CDS is the loss due to the energy in the drain-source output capacitance being dissipated in Q_P at turn-on:

P_SW is the turn-on voltage-current transition loss that occurs as the drain-source voltage decreases and the drain current increases during the turn-on transition:

where I_DRV is the maximum drive current capability of the MAX17690's NDRV pin and I_QP(t-ON) is the instantaneous current in Q_P at turn-on. Because the flyback converter is operating in DCM, I_QP(t-ON) is zero and so is P_SW.

Step 11: Select the RCD Snubber Components

Referring to Figure 8, when Q_P turns off, I_LP charges the output capacitance, C_OSS, of Q_P. When the voltage across C_OSS exceeds the input voltage plus the reflected secondary to primary voltage, the secondary-side diode (or synchronous MOSFET) turns on. Because the diode (or synchronous MOSFET) is now on, the energy stored in the primary magnetizing inductance is transferred to the secondary; however, the energy stored in the leakage inductance continues to charge C_OSS since there is nowhere else for it to go. Because the voltage across C_OSS is the same as the voltage across Q_P, if the energy stored in the leakage inductance charges C_OSS to a voltage level greater than the maximum allowable drain-source voltage of Q_P, the MOSFET Q_P can fail.

One way to keep this situation from arising is to add a suitable RCD snubber across the transformer's primary winding. In Figure 8, the RCD snubber is labeled R_SN, C_SN, and D_SN.

In this situation, when Q_P turns off, the voltage at Node A is:

When the secondary-side diode (or synchronous MOSFET) turns on, the voltage at Node B is:

So, the voltage across the leakage inductance is:

So:

The average power dissipated in the snubber network is:

Substituting Δt_SN into this expression gives:

The leakage inductance energy is dissipated in R_SN, so from:

We can calculate the required R_SN as follows:

Over one switching cycle we must have:

So, we can calculate the required C_SN as follows:

Generally, ΔV_CSN should be kept to approximately 10% to 30% of V_CSN. Figure 9 illustrates V_CSN, ΔI_SN, and Δt_SN. The voltage across the snubber capacitor, V_CSN, should be selected so that:

Choosing too large a value for V_CSN causes the voltage on the drain of Q_P to get too close its maximum allowable drain-source voltage, while choosing too small a value results in higher power losses in the snubber resistor. A reasonable value should result in a maximum drain-source voltage for Q_P that is approximately 75% of its maximum allowable value. The worst-case condition for the snubber circuit occurs at maximum output power when:

Assuming the leakage inductance is 1.5% of the primary inductance, then choosing V_CSN = 54V and ΔV_CSN = 5.4V, we get the following approximate values:

P_SN = 188mW

R_SN = 15.4kΩ

C_SN = 4.7nF

Finally, we consider the snubber diode, D_SN. This diode should have at least the same voltage rating as the MOSFET, Q_P. Although the average forward current is very low, it must have a peak repetitive current rating greater than ΔI_LP(MAX).

Step 12: Calculate the Required Current-Sense Resistor

From Step 4 we have the maximum input power given by:

For the DCM flyback converter all the energy stored in the primary magnetizing inductance, L_P, during the MOSFET on-time is transferred to the output during the MOSFET off-time, i.e., the full power transfer occurs during one switching cycle. Therefore, since E = P × t, we have:

The maximum input energy must be stored in L_P during the on-time of the primary-side MOSFET, so:

Substituting the equations above:

and:

From Step 2 we have:

so:

A standard 60mΩ resistor was chosen for R_CS.

Step 13: Calculate and Select the Input Capacitors

Figure 10 shows a simplified schematic of the primary side of the flyback converter and the associated current waveforms. In steady-state operation, the converter draws a pulsed high-frequency current from the input capacitor, C_IN. This current leads to a high-frequency ripple voltage across the capacitor according to the following expression:

It is the ripple voltage arising from the amp-second product through the input capacitor.

During the Q_P on-time interval from t₀ to t₁, the capacitor is supplying current to the primary inductance L_P of the flyback transformer and its voltage is decreasing. During the Q_P off-time time interval from t₁ to t₂, no current is flowing in L_P, and current is being supplied to the capacitor from the input voltage source. According to the charge balance law, the decrease in capacitor voltage during time t₀ to t₁ must equal the increase in capacitor voltage during time t₁ to t₂. So:

And finally, since:

we have:

For maximum high-frequency ripple voltage requirement ΔV_CIN, we can now calculate the required minimum C_IN. There is high-frequency AC current flowing in C_IN, as shown in the center waveform of Figure 10. The selected capacitor must be specified to tolerate the maximum RMS current, I_CIN(RMS). From the simplified schematic:

Therefore:

where:

and from Step 6:

So:

An additional high-frequency ripple voltage is present due to this RMS current flowing through the ESR of the capacitor. Ceramic capacitors are generally used for limiting high-frequency ripple due to their high AC current capability and low ESR.

In addition to using a ceramic capacitor for high-frequency input ripple-voltage control as previously described, an electrolytic capacitor is sometimes inserted at the input of a flyback converter to limit the input voltage deviation when there is a rapid output load change. A 100% load change gives rise to an input current transient of:

During this transient, there is a voltage drop across any series stray inductance, L_IN(STRAY), that exists between the input voltage source and the input capacitor of the power supply. So from:

we have:

We now have two values for C_IN. One for input high-frequency ripple-voltage control:

and a second for transient input voltage control:

If C_IN(ELE) > C_IN(CER), both ceramic and electrolytic capacitors must be used at the input of the power supply and ΔV_CIN should be limited to approximately 75mV to keep the AC current in the ESR of the electrolytic capacitor within acceptable limits. Otherwise, C_IN(ELE) is not required. In this case, the value of C_IN(CER) can be significantly reduced because there is no longer any requirement to limit ΔV_CIN to less than 75mV. Based on the current design specification with L_IN(STRAY) approximated at 50nH:

C_IN(CER) ≈ 16.3μF

and:

C_IN(ELE) ≈ 1μF

Since C_IN(ELE) < C_IN(CER), an electrolytic capacitor is not required. We can now recalculate C_IN(CER) based on a ΔV_CIN = 600mV:

C_IN(CER) ≈ 2μF

Allowing for a capacitor tolerance of ±10% and a further reduction of capacitance of 70% due to the DC bias effect (operating an 80V ceramic capacitor at 50V), the final nominal value of input capacitance required is:

This is achieved using two 4.7μF ceramic capacitors (Murata GRM32ER71K475KE14) in parallel. The AC current in each capacitor is:

which is well within specification for the selected capacitor.

Step 14: Calculate and Select the Output Capacitor

High-frequency ripple voltage requirements are also used to determine the value of the output capacitor in a flyback converter.

Figure 11 shows a simplified schematic of the secondary side of the flyback converter and the associated current waveforms.

In steady-state operation, the load draws a DC current from the secondary side of the flyback converter. By examining the secondary current waveforms, we see that C_O is supplying the full output current I_OUT to the load during the time interval from t₂ to t₃. During this time interval, the voltage across C_O decreases. At time t₃, Q_P has just turned off and the secondary rectifying diode D_FR (or the secondary synchronous MOSFET Q_S) starts to conduct supplying current to the load and to C_O. The charging and discharging of C_O leads to a high-frequency ripple voltage at the output according to the following expression:

Again, as with the input capacitor, this is the ripple voltage arising from the amp-second product through the output capacitor.

By the capacitor charge balance law, the decrease in capacitor voltage during time t₂ to t₃ must equal the increase in capacitor voltage during time t₁ to t₂. When the capacitor is discharging, we have:

Finally, since:

We have:

For maximum high-frequency ripple voltage requirement ΔV_CO, we can now calculate the required minimum C_O.

C_O ≈ 106.6μF

As with the input capacitor, an additional high-frequency ripple voltage occurs at the output due to the output capacitor's ESR and can be minimized by choosing a capacitor with low ESR. Also, as with the input capacitor, there is high-frequency AC current flowing in C_O as shown in the center waveform of Figure 11. The selected capacitor must be specified to tolerate this maximum RMS current, I_CO(RMS). From the simplified schematic:

Therefore:

where:

and from Step 7:

so:

If we allow for a capacitor tolerance of ±20% and a further reduction of capacitance of 57% due to the DC bias effect (operating a 25V ceramic capacitor at 12V), our final nominal value is:

We can achieve this by placing three 100μF ceramic capacitors (Murata GRM32ER71E226ME15) in parallel. The minimum output capacitance using the above combination is 103.2μF. The AC current in each capacitor is therefore:

which is well within specification for the selected capacitor.

Step 15: Summarize the Power Component Design

A first pass at calculating the power components in the no-opto flyback converter using MAX17690 has been completed. Referring to the schematic, a summary of the power components is listed below:

Part II: Setting Up the MAX17690 No-Opto Flyback Controller

Step 16: Setting Up the Switching Frequency

The MAX17690 can operate at switching frequencies between 50kHz and 250kHz (subject to the considerations in Step 3). A lower switching frequency optimizes the design for efficiency, whereas increasing the switching frequency allows for smaller inductive and capacitive components sizes and costs. A switching frequency of 143.5kHz was chosen in Step 3. R9 sets the switching frequency according to the following expression:

where R9 is in kΩ and f_SW is in Hz.

Step 17: Setting Up the Soft-Start Time

The capacitor C6 connected between the SS pin and SGND programs the soft-start time. A precision internal 5μA current source charges the soft-start capacitor C6. During the soft-start time, the voltage at the SS pin is used as a reference for the internal error amplifier during startup. The soft-start feature reduces inrush current during startup. Since the reference voltage for the internal error amplifier is ramping up linearly, so too is the output voltage during soft-start. The soft-start capacitor is chosen based on the required soft-start time (20ms) as follows:

C6 = 5 × t_ss ≈ 50nF

where C6 is in nF and t_ss is in ms. A standard 47nF capacitor was chosen.

Step 18: Setting Up the UVLO and OVI Resistors

A resistor-divider network of R1, R3, and R2 from V_IN to SGND sets the input undervoltage lockout threshold and the output overvoltage inhibit threshold. The MAX17690 does not commence its startup operation until the voltage on the EN/UVLO pin (R3/R2 node) exceeds 1.215V (typical). When the voltage on the OVI pin (R1/R3 node) exceeds 1.215V (typical), the MAX17690 stops switching, thus inhibiting the output. Both pins have hysteresis built in to avoid unstable turn-on/turn-off at the UVLO/EN and OVI thresholds. After the device is enabled, if the voltage on the UVLO/EN pin drops below 1.1V (typical), the controller turns off; after the device is OVI inhibited, it turns back on when the voltage at the OVI pin drops below 1.1V (typical).

Whenever the controller turns on, it goes through the soft-start sequence. For the current design R1 = 10kΩ, R2 = 481kΩ, and R3 = 11kΩ give rise to an UVLO/EN threshold of 29V and an OVI threshold of 61V.

Step 19: Placing Decoupling Capacitors on V_IN and INTVCC

As previously discussed, the MAX17690 no-opto flyback controller compares the voltage V_FLYBACK to V_IN. This voltage difference is converted to a proportional current that flows in R5. The voltage across R5 is sampled and compared to an internal reference by the error amplifier. The output of the error amplifier is used to regulate the output voltage. The V_IN pin should be directly connected to the input voltage supply. For robust and accurate operation, a ceramic capacitor (C2 = 1μF) should be placed between V_IN and SGND as close as possible to the IC.

V_IN powers the MAX17690's internal low dropout regulator. The LDO's regulated output is connected to the INTVCC pin. A ceramic capacitor (C3 = 2.2μF min) should be connected between the INTVCC and PGND pins for stable operation over the full temperature range. Place this capacitor as close as possible to the IC.

Step 20: Setting Up the Feedback Components

R_SET (R5), R_FB (R4, R110), R_RIN (R8), R_VCM (R6), and R_TC (R105) are all critically important to achieving optimum output voltage regulation across all specified line, load and temperature ranges.

R_SET resistor (R5): This resistor value is optimized based on the IC's internal voltage to current amplifier and should not be changed.

R5 = R_SET = 10kΩ

R_FB resistor (R4, R110): The feedback resistor is calculated according to the previous equation, restated below:

≈ 236.2kΩ

From the MAX17690 data sheet, V_SET = 1V. The two resistors R4 = 182kΩ and R110 = 54.9kΩ form R_FB. Using one high value resistor and one low value resistor in series allows slight adjustment to the series resistance combination so that the output voltage can be fine-tuned to its required value, if necessary.

R_RIN resistor (R8): The internal temperature compensation circuitry requires a current proportional to V_IN to operate correctly. R_RIN establishes this current. R_RIN is calculated according to the following equation:

R_RIN ≈ 0.6 × R_FB

R_VCM resistor (R6): The MAX17690 generates an internal voltage proportional to the on-time volt-second product. This enables the device to determine the correct sampling instant for V_FLYBACK during the Q_P off-time. Resistor R6 is used to scale this internal voltage to an acceptable internal voltage limit in the device. To calculate the resistor, we must first calculate a scaling constant as follows:

After K_C is calculated, the R6 value can be selected from the following table by choosing the resistance value that corresponds to the next largest K_C:

In the present case, R6 = 121kΩ.

R_TC resistor (R105): The value of R_TC can then be calculated using the previous expression, restated by the following:

This completes the setup of the MAX17690 no-opto flyback controller.

Part III: Closing the Control Loop

Step 21: Determine the Required Bandwidth

The bandwidth of the control loop determines how quickly the converter can respond to changes at its input and output. If we have a step change in output current, the voltage across the output capacitor decreases as shown in Figure 12.

The control loop detects this reduction in output voltage and increases the duty cycle of Q_P to supply more current to the output capacitor. The amount of time required by the control loop to increase the duty cycle from its minimum value to its maximum value is the response time, τ_RES, of the control loop. For the MAX17690 we have:

where f_C is the bandwidth of the power converter. If we apply a switching load step of amplitude ΔI_STEP at a frequency of (1/τ_RES) and a 50% duty cycle, then to limit the output voltage deviation to ±ΔV_OUT(STEP) we must have a minimum output capacitance of:

Combining the two previous equations, we have:

It is normal to specify ΔV_OUT(STEP) for a load step from 50% to 100% of the maximum output current. We have already calculated C_O(MIN) = 103.2μF in Step 14, f_SW = 143.3kHz, so based on a 3% maximum ΔV_OUT(STEP):

f_C ≈ 8.9kHz

Step 22: Calculate the Loop Compensation

The MAX17690 uses peak current-mode control and an internal transconductance error amplifier to compensate the control loop. The control loop is modeled, as shown in Figure 13, by a power modulator transfer function G_MOD(s), an output-voltage feedback transfer function G_FB(s), and an error amplifier transfer function G_EA(s).

The power modulator has a pole located at f_P(MOD) determined by the impedance of the output capacitor C_O and the load impedance R_L. It also has a zero at f_Z(MOD) determined by the impedance of C_O and the ESR of C_O. The DC gain of the power modulator is determined by the peak primary current ΔI_LP and the current-sense resistor R_CS. So:

and:

The output voltage feedback transfer function G_FB(s) is independent of frequency and has a DC gain determined by V_IN, V_FLYBACK, and V_SET as follows:

The MAX17690's transconductance error amplifier should be set up in a configuration to compensate for the pole at f_P(MOD) and the zero at f_Z(MOD) of the modulator. This can be achieved by Type II transconductance error amplifier compensation shown in Figure 14.

This type of compensation scheme has a low frequency pole at f_P-LF(EA) due to the very large output resistance R_O (30MΩ – 50MΩ) of the operational transconductance amplifier (OTA). It has a zero at f_Z(EA) determined by C_Z and R_Z of the compensation network, and it has an additional pole at f_P(EA) determined by C_P and R_Z of the compensation network. So:

and:

To achieve stable operation, we must ensure that:

Set the closed loop gain at f_C equal to 1:

Place the zero in the error amplifier network at the same frequency as the pole in the power modulator transfer function:

The frequency f_Z(MOD) at which the zero occurs in the power modulator transfer function depends on the ESR of C_O. If ceramic capacitors are used for C_O, f_Z(MOD) will generally be much higher than f_C. However, if the ESR of C_O is large, f_Z(MOD) could be lower than f_C. This is a very important point since both the gain of the power modulator at f_C, and the gain of the error amplifier at f_C depend on whether f_Z(MOD) is greater than or less than f_C. This is illustrated in Figure 15.

By examining the gain plots in Figure 15, we see that for f_Z(MOD) > f_C:

and for f_Z(MOD) < f_C:

For the current design, we have:

and:

Since f_Z(MOD) > f_C:

and since G_FB is independent of frequency, we have:

We can now set the closed-loop gain equal to 1 as follows:

Rearranging we can calculate:

Substituting ΔI_LP from Step 12:

Finally, we can calculate the remaining components, C_Z and C_P, in the error amplifier compensation network as follows:

and: