MAXREFDES1004

The MAX668/MAX669 constant-frequency, pulse-width modulating (PWM), current-mode DC-DC controllers are designed for a wide range of DC-DC conversion applications, including step-up, SEPIC, flyback, and isolated-output configurations. Power levels of 20W or more can be controlled with conversion efficiencies of over 90%. The input voltage range of 1.8V to 28V supports a wide range of battery and AC-powered inputs. An advanced BiCMOS design features low operating current (220µA), adjustable operating frequency (100kHz to 500kHz), soft-start, and a SYNC input, allowing the MAX668/MAX669 oscillator to be locked to an external clock.

The MAX669 is optimized for low input voltages with a guaranteed start-up voltage of 1.8V. It requires bootstrapped operation (IC-powered from boosted output) and supports output voltages of up to 28V. The MAX668 operates with inputs as low as 3V and can be connected in either a bootstrapped or non-bootstrapped (IC-powered from input supply or other source) configuration. When not bootstrapped, it has no restriction on output voltage. Both ICs are available in an extremely compact 10-pin µMAX® package.

Benefits and Features

• 1.8V Minimum Start-Up Voltage (MAX669)
• Wide Input Voltage Range (1.8V to 28V)
• Tiny 10-Pin µMAX Package
• Current-Mode PWM and Idle Mode Operation
• Adjustable 100kHz to 500kHz Oscillator or SYNC Input
• 220µA Quiescent Current
• Logic-Level Shutdown
• Soft-Start

A negative input, positive output DC-DC converter using the MAX668 is demonstrated for a 5V DC output application. The power supply delivers up to 100mA at 5V. An overview of the design specification is shown in Table 1 below.

This reference design describes the hardware shown in Figure 1. It provides a detailed systematic technical guide to design a negative input, positive output boost converter using Maxim’s MAX668 current mode controller. The power supply has been built and tested, details of which follow later in this document.

A boost converter (step-up converter) is a DC-DC power converter that steps up voltage (while stepping down current) from its input to its output. The key principle that drives the boost converter is the tendency of an inductor to resist changes in current by creating and destroying a magnetic field. In a boost converter, the output voltage is always higher than the input voltage. A schematic of a boost power stage is shown in Figure 2.

Figure 3 shows that when the switch is on, current flows through the inductor in a clockwise direction and the inductor stores some energy by generating a magnetic field. The polarity of the left side of the inductor is positive. During this period, the diode D1 is reverse bias, so there’s no current flow through the diode.

Figure 4 shows that when the switch is off, current is reduced as the impedance is higher. The magnetic field previously created is destroyed to maintain the current toward the load. Thus, the polarity is reversed (meaning the left side of the inductor is negative). As a result, two sources are in series, causing a higher voltage to charge the capacitor through the diode D1.

In a steady-state operating condition, the average voltage across the inductor over the entire switching cycle is zero. This implies that the average current through the inductor is also in a steady state. This is an important rule governing all inductor-based switching topologies. Taking this one step further, we can establish that for a given charge time, t_ON, and a given input voltage and with the circuit in equilibrium, there is a specific discharge time, t_OFF, for an output voltage. Because the average inductor voltage in steady state must equal zero, we can calculate for the boost circuit as follows:

V_IN x t_ON = t_OFF x V_L

And because:

V_OUT = V_IN + V_L

we can then establish the following relationship:

Using the relationship for duty cycle (D):

Then for the boost circuit:

Now that the principle of operation of the boost is understood, a practical design example can be illustrated. The converter design process can be divided into several stages: negative input, positive output boost design, power stage design, and setup of the MAX668 boost current mode controller. This document is primarily concerned with the negative input stage. Positive output boost design, the power stage design, and the other circuit is intended to complement the information contained in the MAX668 data sheet with details on how to set up the protection functions of the controller.

The following design parameters are used throughout:

The above symbols are sometimes followed by parentheses to indicate whether minimum or maximum values of the parameters are intended, for example: minimum input voltage is intended by the symbol V_IN(MIN). Otherwise typical values are intended. In addition, through the design procedure, reference is made to the schematic in another document.

Step 1: Negative Input, Positive Output Boost Design

Figure 5 is a schematic of the negative input, positive output boost converter. Because the input voltage range is -73V to -35V, which is negative, and its absolute value is much higher than the input voltage range of the MAX668, it's necessary to connect the negative input voltage to the ground of MAX668 and use a resistor (R1), a capacitor (C1), and a 6.2V Zener diode to supply the MAX668.

Two PNP transistors level shift a feedback signal from the 5V output to the IC’s FB input. The two PNP transistors Q1 and Q2 are always on, so V2 is approximately 0.5V lower than the ground while V1 is 0.5V higher than V2. That is, the voltage of V1 is the same as the ground voltage. So, the voltage on R3 is the output voltage that we want. As long as the current flow through R3 doesn’t change, the output voltage would be a steady voltage that we can set. The feedback input voltage V_FB of the MAX668 is 1.25V, so the current that flows through R5 is V_FB/R5. As the emitter current and collector current of Q1 are equal, we can conclude that V_OUT/R3 = V_FB/R5. This equation could be used to set the output voltage. For example, assume the output voltage is 5V, R5 = 1.25kΩ, and V_FB = 1.25V, then R3 = 5kΩ.

Step 2: Set the Switching Frequency

The oscillator frequency is set by a resistor, R_OSC, connected from FREQ to GND. R_OSC must be connected, whether or not the part is externally synchronized R_OSC is in each case:

The 125kHz operating frequency, for example, is set with R_OSC = 400kΩ.

Step 3: "Digital" Soft-Start

The MAX668/MAX669 feature a “digital” soft start, which is preset and requires no external capacitor. Upon startup, in five steps over 1024 cycles of f_OSC or f_SYNC, the peak inductor increments from 1/5 of the value set by R_CS to the full current-limit value. For example, with an f_OSC of 200kHz, the complete soft-start sequence takes 5ms.

Step 4: Determining Inductance Value

For most MAX668/MAX669 boost designs, the inductor value (L_IDEAL) can be derived from the following equation, which picks the optimum value for stability based on the MAX668/MAX669’s internally set slope compensation:

The MAX668/MAX669 allow significant latitude in inductor selection if L_IDEAL is not a convenient value. This might happen if L_IDEAL is a not a standard inductance (such as 10µH, 22µH, etc.) or if L_IDEAL is too large to be obtained with suitable resistance and saturation-current rating in the desired size. Inductance values smaller than L_IDEAL can be used with no adverse stability effects; however, the peak-to-peak inductor current (I_LPP) rises as L is reduced. This has the effect of raising the required I_LPK for a given output power and requiring larger output capacitance to maintain a given output ripple. An inductance value larger than L_IDEAL can also be used, but output-filter capacitance must be increased by the same proportion that L has to L_IDEAL. See the Step 9: Output Capacitor Selection section for more information on determining output filter values. Due to the MAX668/ MAX669’s high switching frequencies, inductors with a ferrite core or equivalent are recommended. Powdered iron cores are not recommended due to their high losses at frequencies over 50kHz.

Step 5: Determining Peak Inductor Current

The peak inductor current required for a particular output is:

where I_LDC is the average DC input current and I_LPP is the inductor peak-to-peak ripple current. The I_LDC and I_LPP terms are determined as follows:

where V_D is the forward voltage drop across the Schottky rectifier diode (D1), and V_SW is the drop across the external FET, when on.

Once the peak inductor current is selected, the current-sense resistor (R_CS) is determined by:

Step 6: Power MOSFET Selection

The MAX668/MAX669 drive a wide variety of N-channel power MOSFETs (NFETs). Because LDO limits the EXT output gate drive to no more than 5V, a logic-level NFET is required. Best performance, especially at low input voltages (below 5V), is achieved with low-threshold NFETs that specify on-resistance with a gate-source voltage (V_GS) of 2.7V or less. When selecting an NFET, key parameters can include:

• Total gate charge (Q_g)
• Reverse transfer capacitance or charge (C_RSS)
• On-resistance (R_DS(ON))
• Maximum drain-to-source voltage (V_DS(MAX))
• Minimum threshold voltage (V_TH(MIN))

At high switching rates, dynamic characteristics (parameter 1 and parameter 2 above) that predict switching losses might have more impact on efficiency than R_DS(ON), which predicts DC losses. Q_g includes all capacitances associated with charging the gate. In addition, this parameter helps predict the current needed to drive the gate at the selected operating frequency. The continuous LDO current for the FET gate is:

I_GATE = Q_g x f_OSC

For example, the MMFT3055L has a typical Q_g of 7nC (at V_GS = 5V); therefore, the I_GATE current at 500kHz is 3.5mA. Use the FET manufacturer’s typical value for Q_g in the above equation, since a maximum value (if supplied) is usually too conservative to be of use in estimating I_GATE.

Step 7: Diode Selection

The MAX668/MAX669’s high switching frequency demands a high-speed rectifier. Schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. Ensure that the diode’s average current rating is adequate using the diode manufacturer’s data, or approximate it with the following formula:

Also, the diode reverse breakdown voltage must exceed V_OUT. For high output voltages (50V or above), Schottky diodes might not be practical because of this voltage requirement. In these cases, use a high-speed silicon rectifier with adequate reverse voltage.

Step 9: Output Capacitor Selection

The minimum output filter capacitance that ensures stability is determined using the following formula:

where V_IN(MIN) is the minimum expected input voltage. Typically C_OUT(MIN), though sufficient for stability, is not adequate for low output voltage ripple. Because output ripple in boost DC-DC designs is dominated by capacitor equivalent series resistance (ESR), a capacitance value 2 or 3 times larger than C_OUT(MIN) is typically needed. Low-ESR types must be used. Output ripple due to ESR is:

V_RIPPLE(ESR) = I_PEAK x ESR_COUT

Step 10: Input Capacitor Selection

The input capacitor (C_IN) in boost designs reduces the current peaks drawn from the input supply and reduces noise injection. The value of C_IN is largely determined by the source impedance of the input supply. High source impedance requires high input capacitance, particularly as the input voltage falls. Because step-up DC-DC converters act as “constant-power” loads to their input supply, input current rises as input voltage falls. Consequently, in low-input-voltage designs, increasing C_IN and/or lowering its ESR can add as many as 5 percentage points to conversion efficiency. A good starting point is to use the same capacitance value for C_IN as for C_OUT.

Trademarks

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