Data Sheet Errata
Documentation Errata for ADSP-BF60x Blackfin® Processor Hardware Reference
Doc ID: DOC-1747
Change
Step 6 in the System Interrupt Flow procedure is incorrect.
Current:
The SEC compares the SEC_CPND[n](B) register value to the SEC_CACT[n](A) register value. If the SEC_CACT[n] (A) register value is a higher priority, continue.
Change to:
The SEC compares the SEC_CPND[n](B) register value to the SEC_CACT[n](A) register value. If the SEC_CPND[n](B) register value is a higher priority, continue.
Doc ID: DOC-1467
Change
The description of the SEC_GSTAT.ADRERR
bit is not correct. Change the text as follows (red, strikethrough text is deleted, and blue, underlined text is inserted)
TheSEC_GSTAT.ADRERR
bit indicates that the SECgenerated anddetected an address error (either an access to an invalid address or write to a read-only SEC register). This status bit is sticky; write-1-to-clear it.
Doc ID: DOC-1441
Change
The address translation tables for the DDR2 and LPDDR SDRAMs of the Dynamic Memory Controller are missing. There are separate tables for page and bank interleaving address translation, as follows.
Note: The memory interface is 16 bits; individual DDR2 or LPDDR SDRAM width is 16x.
DDR2 Bank Interleaving Address Translation
DDR2 Bank |
Total Size per External Rank |
Column Address Bits |
Row Address Bits |
Bank Address Bits |
---|---|---|---|---|
256 Mbit | 32 Mbytes | 9:1 | 22:10 | 24:23 |
512 Mbit | 64 Mbytes | 10:1 | 23:11 | 25:24 |
1 Gbit | 128 Mbytes | 10:1 | 23:11 | 26:24 |
2 Gbit | 256 Mbytes | 10:1 | 24:11 | 27:25 |
DDR2 Page Interleaving Address Translation
DDR2 Bank |
Total Size per External Rank |
Column Address Bits |
Row Address Bits |
Bank Address Bits |
---|---|---|---|---|
256 Mbit | 32 Mbytes | 9:1 | 11:10 | 24:12 |
512 Mbit | 64 Mbytes | 10:1 | 12:11 | 25:13 |
1 Gbit | 128 Mbytes | 10:1 | 13:11 | 26:14 |
2 Gbit | 256 Mbytes | 10:1 | 13:11 | 27:14 |
LPDDR Bank Interleaving Address Translation
LPDDR Bank |
Total Size per External Rank |
Column Address Bits |
Row Address Bits |
Bank Address Bits |
---|---|---|---|---|
64 Mbit | 8 Mbytes | 8:1 | 20:9 | 22:21 |
128 Mbit | 16 Mbytes | 9:1 | 21:10 | 23:22 |
256 Mbit | 32 Mbytes | 9:1 | 22:10 | 24:23 |
512 Mbit | 64 Mbytes | 10:1 | 23:11 | 25:24 |
1 Gbit | 128 Mbytes | 10:1 | 24:11 | 26:25 |
2 Gbit | 256 Mbytes | 11:1 | 25:12 | 27:26 |
LPDDR Page Interleaving Address Translation
LPDDR Bank |
Total Size per External Rank |
Column Address Bits |
Row Address Bits |
Bank Address Bits |
---|---|---|---|---|
64 Mbit | 8 Mbytes | 8:1 | 10:9 | 22:11 |
128 Mbit | 16 Mbytes | 9:1 | 11:10 | 23:12 |
256 Mbit | 32 Mbytes | 9:1 | 11:10 | 24:12 |
512 Mbit | 64 Mbytes | 10:1 | 12:11 | 25:13 |
1 Gbit | 128 Mbytes | 10:1 | 12:11 | 26:13 |
2 GBit | 256 Mbytes | 11:1 | 13:12 | 27:14 |
Doc ID: DOC-1434
Change
The descriptions of the DQODS
bits in the DMC_PADCTL
register are incorrect.
The correct descriptions are:
Bit No. (Access) |
Bit Name | Description/Enumeration | |
---|---|---|---|
1:0 (R/W) | DQODS | DQ Output Drive Strength. The DMC_PADCTL.DQODS bits select the output drive strength for the DQ pads.
Note that DMC_PADCTL.DQODS[0] is connected to S1 of PAD, and DMC_PADCTL.DQODS[1] is connected to S0 of PAD. |
|
0 | SSTL18 full drive / LPDDR 10mA | ||
1 | SSTL 18 half drive / LPDDR 4mA | ||
2 | LPDDR 8mA – Reserved for DDR2 mode | ||
3 | LPDDR 2mA – Reserved for DDR2 mode |
Doc ID: DOC-1386
Change
The section will be added in a future revision of this book to document pin multiplexing confgurations.
ADSP-BF60x PORT 349-Ball CSP_BGA GP I/O Multiplexing
When a pin is in peripheral mode (not GPIO mode), the PORT_MUX register controls which peripheral takes ownership of a pin. The Portx Signal Muxing tables show the relationship between the PORT_MUX.MUXn bit fields and their values (function number), the PORT_FER.Pxn bits, and the multiplexed pin functions these bits select.
For all port pins, when the peripheral mode is enabled ( PORT_FER.Pxn =1), the value in the PORT_MUX.MUXn bit fields select the pin function:
00 = default/reset peripheral option
01 = first alternate peripheral option
10 =second alternate peripheral option
11 = third alternate peripheral option
Note:
For information about Input Tap functionality, see the descriptions in chapters corresponding to each input tap pin.
PORTA_MUX.MUXn Bit Field |
Function: GPIO (MUX=x, FER=0) |
Function: 0 (MUX=0, FER=1) |
Function: 1 (MUX=1, FER=1) |
Function: 2 (MUX=2, FER=1) |
Function: Input Tap (MUX=x, FER=x) |
---|---|---|---|---|---|
MUX0 |
PA_00 |
SMC0_A03 |
PPI2_D00 |
LP0_D0 |
|
MUX1 |
PA_01 |
SMC0_A04 |
PPI2_D01 |
LP0_D1 |
|
MUX2 |
PA_02 |
SMC0_A05 |
PPI2_D02 |
LP0_D2 |
|
MUX3 |
PA_03 |
SMC0_A06 |
PPI2_D03 |
LP0_D3 |
|
MUX4 |
PA_04 |
SMC0_A07 |
PPI2_D04 |
LP0_D4 |
|
MUX5 |
PA_05 |
SMC0_A08 |
PPI2_D05 |
LP0_D5 |
|
MUX6 |
PA_06 |
SMC0_A09 |
PPI2_D06 |
LP0_D6 |
|
MUX7 |
PA_07 |
SMC0_A10 |
PPI2_D07 |
LP0_D7 |
|
MUX8 |
PA_08 |
SMC0_A11 |
PPI2_D08 |
LP1_D0 |
|
MUX9 |
PA_09 |
SMC0_A12 |
PPI2_D09 |
LP1_D1 |
|
MUX10 |
PA_10 |
SMC0_A14 |
PPI2_D10 |
LP1_D2 |
|
MUX11 |
PA_11 |
SMC0_A15 |
PPI2_D11 |
LP1_D3 |
|
MUX12 |
PA_12 |
SMC0_A17 |
PPI2_D12 |
LP1_D4 |
|
MUX13 |
PA_13 |
SMC0_A18 |
PPI2_D13 |
LP1_D5 |
|
MUX14 |
PA_14 |
SMC0_A19 |
PPI2_D14 |
LP1_D6 |
|
MUX15 |
PA_15 |
SMC0_A20 |
PPI2_D15 |
LP1_D7 |
|
PORTB_MUX.MUXn Bit Field |
Function: GPIO (MUX=x, FER=0) |
Function: 0 (MUX=0, FER=1) |
Function: 1 (MUX=1, FER=1) |
Function: 2 (MUX=2, FER=1) |
Function: Input Tap (MUX=x, FER=x) |
---|---|---|---|---|---|
MUX0 |
PB_00 |
SMC0_NORCLK |
PPI2_CLK |
LP0_CLK |
|
MUX1 |
PB_01 |
SMC0_AMS1 |
PPI2_FS1 |
LP0_ACK |
|
MUX2 |
PB_02 |
SMC0_A13 |
PPI2_FS2 |
LP1_ACK |
|
MUX3 |
PB_03 |
SMC0_A16 |
PPI2_FS3 |
LP1_CLK |
|
MUX4 |
PB_04 |
SMC0_AMS2 |
SMC0_ABE0 |
SPT0_AFS |
|
MUX5 |
PB_05 |
SMC0_AMS3 |
SMC0_ABE1 |
SPT0_ACLK |
|
MUX6 |
PB_06 |
SMC0_A21 |
SPT0_ATDV |
|
TM0_ACLK4 |
MUX7 |
PB_07 |
SMC0_A22 |
PPI2_D16 |
SPT0_BFS |
|
MUX8 |
PB_08 |
SMC0_A23 |
PPI2_D17 |
SPT0_BCLK |
|
MUX9 |
PB_09 |
SMC0_BGH |
|
SPT0_AD0 |
TM0_ACLK2 |
MUX10 |
PB_10 |
SMC0_A24 |
|
SPT0_BD1 |
TM0_ACLK0 |
MUX11 |
PB_11 |
SMC0_A25 |
|
SPT0_BD0 |
TM0_ACLK3 |
MUX12 |
PB_12 |
SMC0_BG |
SPT0_BTDV |
SPT0_AD1 |
TM0_ACLK1 |
MUX13 |
PB_13 |
ETH0_TXEN |
PPI1_FS1 |
|
TM0_ACI6 |
MUX14 |
PB_14 |
ETH0_REFCLK |
PPI1_CLK |
|
|
MUX15 |
PB_15 |
ETH0_PTPPPS |
PPI1_FS3 |
|
|
PORTC_MUX.MUXn Bit Field |
Function: GPIO (MUX=x, FER=0) |
Function: 0 (MUX=0, FER=1) |
Function: 1 (MUX=1, FER=1) |
Function: 2 (MUX=2, FER=1) |
Function: Input Tap (MUX=x, FER=x) |
---|---|---|---|---|---|
MUX0 |
PC_00 |
ETH0_RXD0 |
PPI1_D00 |
|
|
MUX1 |
PC_01 |
ETH0_RXD1 |
PPI1_D01 |
|
|
MUX2 |
PC_02 |
ETH0_TXD0 |
PPI1_D02 |
|
|
MUX3 |
PC_03 |
ETH0_TXD1 |
PPI1_D03 |
|
|
MUX4 |
PC_04 |
|
PPI1_D04 |
|
|
MUX5 |
PC_05 |
ETH0_CRS |
PPI1_D05 |
|
|
MUX6 |
PC_06 |
ETH0_MDC |
PPI1_D06 |
|
|
MUX7 |
PC_07 |
ETH0_MDIO |
PPI1_D07 |
|
|
MUX8 |
PC_08 |
|
PPI1_D08 |
|
|
MUX9 |
PC_09 |
ETH1_PTPPPS |
PPI1_D09 |
|
|
MUX10 |
PC_10 |
|
PPI1_D10 |
|
|
MUX11 |
PC_11 |
|
PPI1_D11 |
ETH_PTPAUXIN |
|
MUX12 |
PC_12 |
SPI0_SEL7 |
PPI1_D12 |
|
|
MUX13 |
PC_13 |
SPI0_SEL6 |
PPI1_D13 |
ETH_PTPCLKIN |
|
MUX14 |
PC_14 |
SPI1_SEL7 |
PPI1_D14 |
|
|
MUX15 |
PC_15 |
SPI0_SEL4 |
PPI1_D15 |
|
|
PORTD_MUX.MUXn Bit Field |
Function: GPIO (MUX=x, FER=0) |
Function: 0 (MUX=0, FER=1) |
Function: 1 (MUX=1, FER=1) |
Function: 2 (MUX=2, FER=1) |
Function: Input Tap (MUX=x, FER=x) |
---|---|---|---|---|---|
MUX0 |
PD_00 |
SPI0_D2 |
PPI1_D16 |
SPI0_SEL3 |
|
MUX1 |
PD_01 |
SPI0_D3 |
PPI1_D17 |
SPI0_SEL2 |
|
MUX2 |
PD_02 |
SPI0_MISO |
|
|
|
MUX3 |
PD_03 |
SPI0_MOSI |
|
|
|
MUX4 |
PD_04 |
SPI0_CLK |
|
|
|
MUX5 |
PD_05 |
SPI1_CLK |
|
|
TM0_ACLK7 |
MUX6 |
PD_06 |
|
PPI1_FS2 |
|
TM0_ACI5 |
MUX7 |
PD_07 |
|
UART0_TX |
|
TM0_ACI3 |
MUX8 |
PD_08 |
|
UART0_RX |
|
TM0_ACI0 |
MUX9 |
PD_09 |
SPI0_SEL5 |
UART0_RTS |
SPI1_SEL4 |
|
MUX10 |
PD_10 |
SPI0_RDY |
UART0_CTS |
SPI1_SEL3 |
|
MUX11 |
PD_11 |
SPI0_SEL1 |
|
|
SPI0_SS |
MUX12 |
PD_12 |
SPI1_SEL1 |
PPI0_D20 |
SPT1_AD1 |
SPI1_SS |
MUX13 |
PD_13 |
SPI1_MOSI |
|
|
TM0_ACLK5 |
MUX14 |
PD_14 |
SPI1_MISO |
|
|
TM0_ACLK6 |
MUX15 |
PD_15 |
SPI1_SEL2 |
PPI0_D21 |
SPT1_AD0 |
|
PORTE_MUX.MUXn Bit Field |
Function: GPIO (MUX=x, FER=0) |
Function: 0 (MUX=0, FER=1) |
Function: 1 (MUX=1, FER=1) |
Function: 2 (MUX=2, FER=1) |
Function: Input Tap (MUX=x, FER=x) |
---|---|---|---|---|---|
MUX0 |
PE_00 |
SPI1_D3 |
PPI0_D18 |
SPT1_BD1 |
|
MUX1 |
PE_01 |
SPI1_D2 |
PPI0_D19 |
SPT1_BD0 |
|
MUX2 |
PE_02 |
SPI1_RDY |
PPI0_D22 |
SPT1_ACLK |
|
MUX3 |
PE_03 |
|
PPI0_D16 |
ACM0_FS/SPT1_BFS |
|
MUX4 |
PE_04 |
|
PPI0_D17 |
ACM0_CLK/SPT1_BCLK |
|
MUX5 |
PE_05 |
|
PPI0_D23 |
SPT1_AFS |
|
MUX6 |
PE_06 |
SPT1_ATDV |
PPI0_FS3 |
LP3_CLK |
|
MUX7 |
PE_07 |
SPT1_BTDV |
PPI0_FS2 |
LP3_ACK |
|
MUX8 |
PE_08 |
PWM0_SYNC |
PPI0_FS1 |
LP2_ACK |
ACM0_T0 |
MUX9 |
PE_09 |
|
PPI0_CLK |
LP2_CLK |
PWM0_TRIP0 |
MUX10 |
PE_10 |
ETH1_MDC |
PWM1_DL |
RSI0_D6 |
|
MUX11 |
PE_11 |
ETH1_MDIO |
PWM1_DH |
RSI0_D7 |
|
MUX12 |
PE_12 |
|
PWM1_CL |
RSI0_D5 |
|
MUX13 |
PE_13 |
ETH1_CRS |
PWM1_CH |
RSI0_D4 |
|
MUX14 |
PE_14 |
|
SPT2_ATDV |
TM0_TMR0 |
|
MUX15 |
PE_15 |
ETH1_RXD1 |
PWM1_BL |
RSI0_D3 |
|
PORTF_MUX.MUXn Bit Field |
Function: GPIO (MUX=x, FER=0) |
Function: 0 (MUX=0, FER=1) |
Function: 1 (MUX=1, FER=1) |
Function: 2 (MUX=2, FER=1) |
Function: Input Tap (MUX=x, FER=x) |
---|---|---|---|---|---|
MUX0 |
PF_00 |
PWM0_AL |
PPI0_D00 |
LP2_D0 |
|
MUX1 |
PF_01 |
PWM0_AH |
PPI0_D01 |
LP2_D1 |
|
MUX2 |
PF_02 |
PWM0_BL |
PPI0_D02 |
LP2_D2 |
|
MUX3 |
PF_03 |
PWM0_BH |
PPI0_D03 |
LP2_D3 |
|
MUX4 |
PF_04 |
PWM0_CL |
PPI0_D04 |
LP2_D4 |
|
MUX5 |
PF_05 |
PWM0_CH |
PPI0_D05 |
LP2_D5 |
|
MUX6 |
PF_06 |
PWM0_DL |
PPI0_D06 |
LP2_D6 |
|
MUX7 |
PF_07 |
PWM0_DH |
PPI0_D07 |
LP2_D7 |
|
MUX8 |
PF_08 |
SPI1_SEL5 |
PPI0_D08 |
LP3_D0 |
|
MUX9 |
PF_09 |
SPI1_SEL6 |
PPI0_D09 |
LP3_D1 |
|
MUX10 |
PF_10 |
ACM0_A4 |
PPI0_D10 |
LP3_D2 |
|
MUX11 |
PF_11 |
|
PPI0_D11 |
LP3_D3 |
PWM0_TRIP1 |
MUX12 |
PF_12 |
ACM0_A2 |
PPI0_D12 |
LP3_D4 |
|
MUX13 |
PF_13 |
ACM0_A3 |
PPI0_D13 |
LP3_D5 |
|
MUX14 |
PF_14 |
ACM0_A0 |
PPI0_D14 |
LP3_D6 |
|
MUX15 |
PF_15 |
ACM0_A1 |
PPI0_D15 |
LP3_D7 |
|
PORTG_MUX.MUXn Bit Field |
Function: GPIO (MUX=x, FER=0) |
Function: 0 (MUX=0, FER=1) |
Function: 1 (MUX=1, FER=1) |
Function: 2 (MUX=2, FER=1) |
Function: Input Tap (MUX=x, FER=x) |
---|---|---|---|---|---|
MUX0 |
PG_00 |
ETH1_RXD0 |
PWM1_BH |
RSI0_D2 |
|
MUX1 |
PG_01 |
SPT2_AFS |
TM0_TMR2 |
CAN0_TX |
|
MUX2 |
PG_02 |
ETH1_TXD1 |
PWM1_AL |
RSI0_D1 |
|
MUX3 |
PG_03 |
ETH1_TXD0 |
PWM1_AH |
RSI0_D0 |
|
MUX4 |
PG_04 |
SPT2_ACLK |
TM0_TMR1 |
CAN0_RX |
TM0_ACI2 |
MUX5 |
PG_05 |
ETH1_TXEN |
RSI0_CMD |
PWM1_SYNC |
ACM0_T1 |
MUX6 |
PG_06 |
ETH1_REFCLK |
RSI0_CLK |
SPT2_BTDV |
PWM1_TRIP0 |
MUX7 |
PG_07 |
SPT2_BFS |
TM0_TMR5 |
|
CNT0_ZM |
MUX8 |
PG_08 |
SPT2_AD1 |
TM0_TMR3 |
|
PWM1_TRIP1 |
MUX9 |
PG_09 |
SPT2_AD0 |
TM0_TMR4 |
|
|
MUX10 |
PG_10 |
UART1_RTS |
SPT2_BCLK |
|
|
MUX11 |
PG_11 |
SPT2_BD1 |
TM0_TMR6 |
|
CNT0_UD |
MUX12 |
PG_12 |
SPT2_BD0 |
TM0_TMR7 |
|
CNT0_DG |
MUX13 |
PG_13 |
UART1_CTS |
|
|
TM0_CLK |
MUX14 |
PG_14 |
UART1_RX |
SYS_IDLE1 |
|
TM0_ACI1 |
MUX15 |
PG_15 |
UART1_TX |
SYS_IDLE0 |
SYS_SLEEP |
TM0_ACI4 |
Doc ID: DOC-1760
Change
For the PWM_CHANCFG
Configuration registers, the timer options are:
- PWMAH \ AL – Timer 0 & Timer 1
- PWMBH \ BL – Timer 0 & Timer 2
- PWMCH \ CL – Timer 0 & Timer 3
- PWMDH \ DL – Timer 0 & Timer 4
In the Table:
For PWM_CHANCFG.REFTMRD
, the bit description should be:
The PWM_CHANCFG.REFTMRD
bit selects whether the PWM uses PWMTMR0 or PWMTMR4 as the reference timer for Channel D operation.
The enumerations description should be:
0 = PWMTMR0 is Channel D reference
1 = PWMTMR4 is Channel D reference
For PWM_CHANCFG.REFTMRC
, the bit description should be:
The PWM_CHANCFG.REFTMRC
bit selects whether the PWM uses PWMTMR0 or PWMTMR3 as the reference timer for Channel C operation.
The enumerations description should be:
0 = PWMTMR0 is Channel C reference
1 = PWMTMR3 is Channel C reference
For PWM_CHANCFG.REFTMRB
, the bit description should be:
The PWM_CHANCFG.REFTMRB
bit selects whether the PWM uses PWMTMR0 or PWMTMR2 as the reference timer for Channel B operation.
The enumerations description should be:
0 = PWMTMR0 is Channel B reference
1 = PWMTMR2 is Channel B reference
Doc ID: DOC-1405
Change
There is a bit description missing in table 22-75, USB_PHY_CTL Register Fields. This is bit 4 (DIS) which has the following description.
DIS, Disable PHY
0 - USB PHY and 5V protection on USB signals enabled.
1 - USB PHY and 5V protection on USB signals disabled. Disabling the PHY and 5V protection results in reduced hibernate current.CAUTION- With 5V protection disabled the absolute max voltage on USB signals is reduced. See the data sheet for details.
Doc ID: DOC-1465
Change
In Table 23-27, Destination Address Filtering, the column labeled HMC contains the DAIF settings, and the column labeled DAIF contains the HMC settings. Using incorrect settings can cause address filtering failures.
Doc ID: DOC-1418
Change
In the description of the Back Off Limit (EMAC_MACCFG.BL) bit, "4,096 bit times for 1000 Mbps" should be removed because the BF60x EMAC supports only 10/100Mbps operation.
Doc ID: DOC-1478
Change
The title of Table 30-21 is incorrect. The correct title is YCbCr 4:2:2 16-Bit Type 1 (CrYCbY) with 10 to 16 Bits per PIXCLK (not UCbCr).
Doc ID: DOC-1483
Change
On page 30-35, in the section "OPFn Data Packing" (second paragraph, first sentence), the text should change from:
The PVP_OPFn_CTL.OSIZE
=0 setting instructs the OPFn block to accept a full 32-bit word from the data source.
Change to:The PVP_OPFn_CTL.ISIZE
=0 setting instructs the OPFn block to accept a full 32-bit word from the data source.
Doc ID: DOC-1485
Change
The statement "The CNVn block supports down scaling by dropping output pixels in both directions.
The PVP_CNVn_SCALE
bits are used to set the horizontal downscale factor, and the PVP_CNVn_SCALE.VSCL
bits are used to set the vertical downscale factor." contains an error.
The horizontal downscale factor is set using PVP_CNVn_SCALE.HSCL
bits, not PVP_CNVn_SCALE
bits.
Doc ID: DOC-1444
Change
In Table 30-47, the description of Continuous Frame mode incorrectly states: Processing Blocks do not auto-disable. New Configuration must not set PVP_xxx_
CFG.START
bit of any block again.
The correct information is: Only IPFn blocks auto-disable, other processing blocks do not. A new configuration
needs to reset START
bit of IPFn, but must not set the START
bit of the other blocks.
Ideally, writes to PVP_xxx_CFG
registers of PVP blocks other than IPFn are avoided altogether.
Note: This behavior is the same as for Back-to-Back mode.
Doc ID: DOC-1439
Change
In figure 30-70 (BSL Example), the figure incorrectly shows the THC1 block status header located in the block status list before the THC0 block status header and the THC0 status words.
The correct location of the THC1 block status header in the block status list is after the THC0 block status header and the THC0 status words.
Doc ID: DOC-1477
Change
In Frame Sync Polarity and Sampling Edge, the title and leftmost column of Table 31-8 are incorrect. The corrected table is as follows:
Table 31-8: Clock Polarity Selections and Receive/Transmit Pin States
Bit Setting | Receive | Transmit | ||
---|---|---|---|---|
Sample Data | Sample/Drive Syncs | Drive Data | Sample/Drive Syncs | |
POLC = b#00 | Falling edge | Falling edge | Rising edge | Rising edge |
POLC = b#01 | Falling edge | Rising edge | Rising edge | Falling edge |
POLC = b#10 | Rising edge | Falling edge | Falling edge | Rising edge |
POLC = b#11 | Rising edge | Rising edge | Falling edge | Falling edge |
Doc ID: DOC-1406
Change
The following formula for calculating the EPPI clock is incorrect:
PPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV + 1))
The correct formula for calculating the EPPI clock is:
PPI_CLK = SCLK/(EPPI_CLKDIV + 1)
Doc ID: DOC-1443
Change
The following equation is incorrect:
PPI_CLK = ( SCLK ) / ( 2 * ( EPPI_CLKDIV + 1 ) )
The correct equation is:
fPCLK = fSCLK / ( EPPI_CLKIV + 1 )
where:
fPCLK
is the frequency of the internally generated EPPI clock.fSCLK
is the frequency ofSCLK
.EPPI_CLKDIV
is the value programmed for clock division in theEPPI_CLKDIV
register.
Doc ID: DOC-1469
Change
Figure 35-7 and Table 35-7 describe bit 3 in the SDU_STAT
register as toggling Secure mode. This information is incorrect. Bit 3 is reserved in ADSP-BF60x processors.
Last Update Date: May 7 2018