Data Sheet Errata
Documentation Errata for ADSP-BF5xx/ADSP-BF60x Blackfin® Processor Programming Reference
Doc ID: DOC-1402
Change
The Core Event Vector Table (Table 4-8) is not correct for BF60x processors because the system interrupt interface to the core connects with the System Event Controller (SEC). For ADSP-BF60x processors, the correct information is as follows:
Name | Event Class | Event Vector Register | MMR Location | Notes |
---|---|---|---|---|
EMU | Emulation | EVT0 | 0xFFE0 2000 | Highest priority. Vector address is provided by JTAG. |
RST | Reset | EVT1 | 0xFFE0 2004 | |
NMI | NMI | EVT2 | 0xFFE0 2008 | |
EVX | Exception | EVT3 | 0xFFE0 200C | |
Reserved | Reserved | EVT4 | 0xFFE0 2010 | Reserved vector |
IVHW | Hardware Error | EVT5 | 0xFFE0 2014 | |
IVTMR | Core Timer | EVT6 | 0xFFE0 2018 | |
IVG7 | Interrupt 7 | EVT7 | 0xFFE0 201C | Software interrupt |
IVG8 | Interrupt 8 | EVT8 | 0xFFE0 2020 | Software interrupt |
IVG9 | Interrupt 9 | EVT9 | 0xFFE0 2024 | Software interrupt |
IVG10 | Interrupt 10 | EVT10 | 0xFFE0 2028 | Software interrupt |
IVG11 | Interrupt 11 | EVT11 | 0xFFE0 202C | All system interrupts through SEC |
IVG12 | Interrupt 12 | EVT12 | 0xFFE0 2030 | Software interrupt |
IVG13 | Interrupt 13 | EVT13 | 0xFFE0 2034 | Software interrupt |
IVG14 | Interrupt 14 | EVT14 | 0xFFE0 2038 | Software interrupt |
IVG15 | Interrupt 15 | EVT15 | 0xFFE0 203C | Software interrupt |
Doc ID: DOC-1502
Change
In IMEM_CONTROL Register, the following information is missing from the discussion of the RDCHK
bit:
Caution: Disabling instruction cache with parity enabled immediately generates parity errors because all valid cache tag bits are invalidated. This behavior is normal even when the RDCHK
bit is cleared in the same write. To prevent the generation of cache tag parity errors:
- Clear the
RDCHK
bit to disable parity checking. - Issue an
SSYNC
instruction. - Clear the
IMC
bit to disable the cache.
Doc ID: DOC-1503
Change
In IMEM_CONTROL Register, the following statements are incorrect:
- The
RDCHK
bits are similar to the cache enable bitsCEN[1:0]
in this register. - The
CBYPASS
bits are similar to the cache enable bitsCEN[1:0]
in this register.
Similarity is with the IMC
bit, not the CEN[1:0]
bits.
Doc ID: DOC-1505
Change
In Instruction Cache Invalidation, the following statement is incorrect:
An SSYNC
instruction should be run before invalidating the cache and a CSYNC
instruction should be inserted after each of these operations.
The correct information is:
An SSYNC
instruction should be run before invalidating the cache and a SSYNC
instruction should be inserted after each of these operations.
Caution: If parity checking is enabled because the RDCHK
bit of the IMEM_CONTROL
register is set:
- Clear the
RDCHK
bit to disable parity checking. - Issue an
SSYNC
instruction. - Clear the
IMC
bit to disable the cache.
Note: Before reenabling cache, reinitialize the cache tag arrays if parity checking is again desired. See DTEST_DATA0 Register on page 6-48.
Doc ID: DOC-1504
Change
In DMEM_CONTROL Register, the following statements are incorrect:
- The
RDCHK
bits are similar to the cache enable bitsCEN[1:0]
in this register. - The
CBYPASS
bits are similar to the cache enable bitsCEN[1:0]
in this register.
Similarity is with the DMC[1:0]
bits, not the CEN[1:0]
bits.
Doc ID: DOC-1470
Change
In Figures 6-23 and 6-24, the description of bit 18 applies only to ADSP-BF60x processors. For ADSP-BF5xx processors, bit 18 is reserved and set to 0, therefore, the encodings for 16KB, 64KB, 16MB, and 64MB in the PAGE_SIZE
field do not apply.
In Figure 6-24, the name of bit 15 is incorrectly given as CPL7B_L1_AOW
. The correct name is CPLB_L1_AOW
.
Doc ID: DOC-1403
Change
In the Miscellaneous section, add the following bullet to the list:
The disabling of the cache causes all cache tags to be invalidated, but the parity bits in the tags are not updated to reflect this change. For this reason any L1 memory used as cache must re-initialized if L1 cache has been enabled and subsequently disabled.
Last Update Date: May 8 2017