Documentation Errata for ADSP-BF561: Blackfin Embedded Symmetric Multiprocessor Data Sheet
Chapter: / Page 20
Doc ID: DOC-902
Footnote 2 of the Operating Conditions table does not apply for 500 MHz models. Change the footnote from:
2 See Ordering Guide on Page 63.Change to:
2 Does not apply to 500 MHz speed grade models. External Voltage regulation is required on automotive grade models (see Ordering Guide on Page 63) to ensure correct operation.
Chapter: / Page 20
Doc ID: DOC-906
In table 9 (Core Clock (CCLK) Requirements -- 500 MHz and 533 MHz Speed Grade Models), change footnote 2 from:
2External Voltage regulation is required on automotive grade models (see Ordering Guide on Page 63) to ensure correct operation.Change to:
2External Voltage regulation is required on automotive grade models to ensure correct operation. Not applicable to 500 MHz speed grade models. See Ordering Guide on Page 63.
Chapter: / Page 34
Doc ID: DOC-1126
The timing specifications for tDDTTE and tDDTTI are not properly documented in Table 25 of the Data sheet. The two specs are only applicable when the SPORT is in Multichannel mode. Also, when in multichannel mode, SPORT TSCLK is internally connected to RSCLK. Therefore, Page 34, Table 25, should read as follows .
|tDTENE||Data Enable Delay from External TSCLKx1||0||ns|
|tDDTTE||Data Disable Delay from External TSCLKx1, 2, 3||10||ns|
|tDTENI||Data Enable Delay from Internal TSCLKx1||-2||ns|
|tDDTTI||Data Disable Delay from Internal TSCLKx1, 2, 3||3||ns|
(1) Referenced to drive edge.
(2) Applicable to multichannel mode only.
(3) TSCLKx is tied to RSCLKx.
Chapter: / Page 39
Doc ID: DOC-1286
Add the following section to the data sheet.
Timer Clock Timing
Switching Characteristic = tTODP: Timer Output Update Delay After PPI_CLK High = 12
Use the timing diagram from the ADSP-BF534/ADSP-BF536/ADSP-BF537 data
There are also three timing specifications (tTIS, tTIH, and tTOD ) that are missing in Table 39 (Timer Cycle Timing) on page 48. Additionally the unit of measure has changed.
Replace the current table with the following table.
|tWL||Timer Pulse Width Input Low1||1 x tSCLK||ns|
|tWH||Timer Pulse Width Input High1||1 x tSCLK||ns|
|tTIS||Timer Input Setup Time Before CLKOUT Low2||6.5||ns|
|tTIH||Timer Input Hold Time After CLKOUT Low2||-1.0||ns|
|tHTO||Timer Pulse Width Output||1 x tSCLK||(232 - 1) x tSCLK||ns|
|tTOD||Timer Output Update Delay After CLKOUT High||6.0||ns|
(1) The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
(2) Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Chapter: N/A / Page 16
Doc ID: DOC-837
Insert the following section after the Related Documents section:
Related Signal Chains
A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the "signal chain" entry in Wikipedia or the Glossary of EE Terms on the Analog Devices website.
Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website.
The Application Signal Chains page in the Circuits from the Labtm site (http:\\www.analog.com\signalchains) provides:
Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications
Drill down links for components in each chain to selection guides and application information
Reference designs applying best practice design techniques
Last Update Date: May 8 2017