Why Choose TigerSHARC Processors for Wireless?

Wireless Infrastructure manufacturers can consider many approaches when developing baseband modem solutions for third generation wireless communications networks (3G), however the TigerSHARC Processor architecture provides the balance of attributes required to satisfy the entire range of challenges facing their 3G deployments. The next generation of baseband processing designs must allow for leading edge performance while retaining a significant level of flexibility in order to adapt not only to the various new CDMA based standards of 3G (WCDMA, CDMA, TD-SCDMA), but also to their inevitable changes and feature enhancements.

The Analog Devices TigerSHARC^® Processor architecture provides the greatest marriage of performance and flexibility enabling the most cost effective solution for baseband processing and other applications within the Wireless Infrastructure market space today.

What are some of the available baseband modem solutions?

Traditional baseband modem designs and popular thought have contributed to the idea that the optimal solution architecture needs to include both an ASIC and a DSP, but now with the advent of the TigerSHARC Processor the time has come to dispel this myth. It has been published in many whitepapers and trade journals that the two components of baseband processing, Chip Rate processing and Symbol Rate processing, need to be portioned in order to realize a cost effective solution. The Chip Rate portion, primarily responsible for voice channel communications, because of the rudimentary correlation operations it possesses, is routinely handled by a hardwired ASIC specifically designed for this task. The Symbol Rate portion, which is associated with data channel communications, presents the need to not only process multiple channels, but also to process very high data rate channels (up to 384 kbps). It is this task of processing multiple channels of differing very high data rates that is tailor made for the performance offered by a programmable DSP. The TigerSHARC Processor provides the base station designer with the capability of what is referred to as "load balancing". "Load Balancing" is the implementation of both the Symbol Rate and the Chip Rate portion of baseband processing in a solution based solely on the TigerSHARC Processor . This is done through the movement of DSP's processing power or MIPS from Symbol Rate to Chip Rate processing depending on the profile of the channel types at any given time.

What makes the TigerSHARC Processor different from other Solutions?

The TigerSHARC Processor architecture provides leading edge throughput capabilities and special acceleration instruction set optimized for Wireless Infrastructure applications that reduce the burden of channel decoding. This task has been historically viewed as impossible to cost-effectively implement in a DSP. The TigerSHARC Processor offers specific instructions targeted to reduce the processing requirements associated with both the Turbo and Viterbi decoding schemes of Forward Error Correction.

Where does the flexibility of the TigerSHARC^® come into play?

The requirement for flexibility within the 3G Wireless Infrastructure market space was discussed earlier in this piece. What better way to deal with the ever changing multiple standards of 3G than with a completely programmable solution? The TigerSHARC Processor is the heart of a software defined solution for baseband modems where all of the implementation occurs in software rather than in hardware as is the approach taken by ASIC and other competing DSP solutions. The TigerSHARC Processor allows for the infrastructure vendor to establish a single baseband processing platform for all of the 3G standards with easily implemented software changes to update functionality and speed time to market.

Are there any other Wireless Infrastructure applications for the TigerSHARC Processor?

The TigerSHARC Processor is also targeted as the solution engine for such other applications as RF Power Amplifiers and Smart Antenna Arrays.

Wireless Base Station architectures are rapidly adopting Multi-Carrier Power Amplifier (MCPA) technology to take advantage of distinct reductions in physical size, cost and power consumption. One issue that is not addressed however in the move from single carrier to multi-carrier power amplifiers is the correction of non-linearities in the amplifier's output. The implementation of linearization solutions to enhance the output from these amplifiers produces significant improvement in the areas of signal strength and interference reduction. There are many different techniques available today, however the use of Adaptive Pre-distortion or Baseband Pre-distortion is seen as the future technique of choice. Adaptive Pre-distortion utilizes DSPs to implement the correction at digital baseband. Analog Devices has developed specific algorithms and instruction for the TigerSHARC Processor that significantly improve the cancellation performance, while reducing system cost with the elimination of some of the costly RF components used in other linearization techniques.

Smart antenna arrays, both the phased and adaptive varieties, are becoming a more widely accepted technology for use in 3G infrastructure deployments. The smart antenna array provides greater power, to increase signal-to-noise ratios, and interference suppression for overall noise reduction. These attributes translate into higher data rates with better coverage for a larger number of users. Analog Devices has produced specific algorithms and instructions for the optimization of beam selection and beamforming to further enhance the performance of smart antennas.

Conclusion

As a result of its "Load Balancing" capabilities, high internal and external bandwidth, large integrated memory and unmatched level of flexibility, the TigerSHARC Processor proves to be an unconventional but extremely effective solution for baseband signal processing. In future generations of the TigerSHARC Processor we intend to continue the trend towards reduced systems cost and component count while increasing the functionality of the solution through clock speed enhancements and an expanded instruction set.