ADRV906x (Samana): The Most Integrated SDR Platform for 4G/5G Networks
ADRV906x (Samana): The Most Integrated SDR Platform for 4G/5G Networks
The ADRV906x (Samana) enables engineers to build compact, energy-efficient, and secure radio units for global mobile networks. This software-defined SoC consolidates RF and digital processing, delivering O-RAN-compliant 7.2x Low PHY with ADI's most integrated, intelligent, and secure radio platform.
The Future of RAN: Smarter, More Energy Efficient, Software-Defined Architecture with Samana
Technical Highlights
One Board, Complete Portfolio:
Configure small cells to macros on a single board with bandwidths from 20 MHz to 400 MHz. Supports all LTE, NR FR1 and NB-IoT bands in TDD, FDD, and mixed-mode operation.- Performance & Efficiency:
Gen-6 ML DPD supports PAs up to 80 W with 600 MHz bandwidth. Neural engine continuously optimizes PA performance for maximum efficiency. - Security & Reliability:
Embedded MACSec, secure boot, and advanced security architecture protect against network threats. - Risk Reduction:
Interoperability-tested, O-RAN stack and reference design reduce design errors and accelerate RU bring-up.
Key Platform Features
Flexibility
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With a software-defined radio unit SOC, a single compact radio board enables a broad portfolio of Small Cell and Macro products.
- Support for all LTE, NR FR1 and NB-IoT bands, single, dual, and tri-band combinations for TDD, FDD, or mixed-mode operation.
- 4T4R/1OR or 8T8R/2OR configuration via Chip-to-Chip Interface.
- Small Cell to Macro Radios – DPD supports PAs from 25 mW up to 80W, up to 600 MHz instantaneous bandwidth.
- Maximum Occupied Bandwidth: 400 MHz Per Antenna.
O-RAN compliant Low PHY/eCPRI stack
- O-RAN compliance: Interoperability-tested 7.2x eCPRI Low PHY stack ready for commercial deployment.
- Integrated Low PHY, and embedded neural-network engine: reduces board size, design complexity, and BOM costs.
Energy Efficiency
Energy efficiency is engineered across the system using multiple, complementary approaches.
- Integrating Low PHY functionality: eliminates or significantly reduces FPGA reducing size, weight, and energy while streamlining the architecture.
- Gen 6 Digital Pre-Distortion (DPD): significantly improves power amplifier efficiency.
- RadioVerse DTx: automated discontinuous transmission (DTx) settings use real-time network traffic data to deliver energy savings exceeding 35% with zero impact on KPIs.
- Symbol-Based Envelope Tracking: dynamically reduces energy consumption by matching PA power levels to actual network traffic in real time complimenting DTx settings without sacrificing performance.
Gen 6 DPD, CFR
- Machine learning-based digital pre-distortion continuously optimizes PA performance.
- Charge trap compensation (CTC) for GaN PAs improves signal quality.
- Supports Power Amplifiers from 25mW to 80W, up to 600MHz instantaneous bandwidth.
Network Security
- MACsec supporting AES-128/AES-256 encryption.
- Integrated support for secure boot, secure update, and life cycle management provided by tiny enclave.
ADRV906x Block Diagram
ADRV9062 is not a standalone product. It needs to be used with the ADRV9061 for an 8T8R configuration.
