Frequently Asked Question
Does the fine delay adjust affect the jitter?
Yes. Because this fine delay adjust is an analog function, it contributes a significant amount of jitter to the clock output on which it is used (but only when it is used; there is no effect on jitter when the delay block is off). The longer the delay, the more the jitter. This is why this type of delay is not provided on all of the outputs.
Users can see this relationship using the free ADIsimCLK software available on the website: www.analog.com/ADIsimCLK
This feature is intended to be used to drive digital devices such as ASICs, FIFOs, FPGAs, etc. where a delay is needed in order to synchronize to digital data. It is not recommended for encode clocks on converters, due to the added jitter.