Instructions for the AD9861/AD9863 Evaluation Board

General Notes

Refer to the AD9861 or the AD9863 datasheets for a more detailed explanation of the device under test (DUT).

A power on reset circuit including a ADM1818 (U11) is connected to the RESET pin on the DUT and will maintain a logic low signal until the 3VDD supply is over its threshold voltage. A push button switch, SW1, is available for asynchronous reset of the DUT. This is shown on Page 3 of the schematic.

The ADC and DAC reference voltages are decoupled very close to the DUT and in some cases on the bottom side of the board.

Components marked as DNI are, by default, not included and act as a component place holder. The evaluation board works with both the AD9861 and AD9863. The different pinouts of the devices is accommodated through jumper and component settings. The AD9861 is shown on page 2 of the schematic.

Power Supply Connections

There are 5 supply connections provided through 4 terminal blocks on the AD9861/AD9863 Evaluation Board. The Terminal Blocks along with decoupling and power plane labels are shown in page 1 and 4 of the schematic.

Terminal Block 1, TB1, requires four connections, a +5V analog supply on pin 3 and associated ground on pin 4 for non-DUT analog support components and a +3V analog supply voltage on pin 1 for the DUT analog power with an associated clean analog ground on pin 2.

TB2 requires two connections, a +3V supply and ground for various on board digital support logic.

TB3 requires two connections a +3V digital supply voltage and associated ground for the DUT digital power.

TB4 requires two connections, a +3V clean supply and ground for on board clock generation circuitry (if used).


The clock source for the evaluation board can be obtained from either the on-board 64 MHz crystal oscillator, U9 or from an external reference connected to the SMA connection, J4 for the AD9861 or J4 and J5 for the AD9863.

These clocks can be used directly or buffered using U12 by setting JP54 and 55 for the AD9861 or JP54, JP55, JP56 and JP39 for the AD9863. The duty cycle of an external reference can be adjusted by changing the bias voltage at the input to the buffer, U12, using the potentiometer, R70. The duty cycle of the CLKIN2 for the AD9863 board can be adjusted by changing the bias voltage on U10 and using the potentiometer, R68.

SPI Port

The SPI port and the Auxiliary SPI port are controlled through the J2 connector and buffered using U13. The J2 connector is a 36 pin micro-Centronics connector that can interface to a PC parallel port using a DB25 Male/Micro Centronics 36 Male Parallel Cable. Signals are shown on page 9 of the schematic.

Receive Path

The input Rx path is shown on page 6 of the schematic and the output signal path is shown on page 7 and 8.

The Rx input paths for channel A or B are independent. The input path can be configured to use an on-board differential driver, drive a transform or drive the Rx inputs directly single ended.

By default, the AD9861/63 internal input circuitry is self biased to half of the DUT AVDD voltage. The self biasing can be disabled by writing to the appropriate register control.

Rx Input without on-board differential driver (transformer or direct):

The Rx input signal is connected to SMA J6 for the Rx channel A and SMA J7 for the Rx channel B. Jumpers JP45, JP46, JP48 and JP49 would be set to jumper legs 2 to 3. Jumpers JP52 and JP53 can be used to configure a single ended input into the Rx path.

Rx Input with on-board differential driver:

The Rx input signal is connected to SMA J12 for the Rx channel A and SMA J11 for the Rx channel B. The signal is buffered using the on-board AD8138, U16 and U17. Jumpers JP45, JP46, JP48 and JP49 should be set to the jumper legs 1 to 2 position. The dc blocking caps (C112, C116, C118 and C119) are used to block the dc output of the AD8138 and allows the Rx path inputs to maintain their the self-biasing voltage.

Rx Output:

The two 10/12 bit buses are buffered on the board using U1 and U3 for the AD9863 and U1 and U4 for the AD9861. The buffers are connected to the 80 pin connector, J1. Also available on this connector are the RxSYNC signal and an optional output clock (the digital bus connections are shown on pages 7 and 8 in the schematic.

Transmit Path

The Tx output path is shown on page 5 of the schematic and the digital input Tx path is shown on pages 7and 8.

The Tx output paths for channel A or B are independent and can be viewed differentially between JP3 and JP6 for Tx channel A and between JP10 and JP11 for Tx channel B. The output can also be view single ended (after a transformer) at SMA S3 and S2. Each of the output pins has 50 ohm termination to ground which will proved a 0 to 1 V swing for each pin under 20 mA full scale current. An optional AD8345, U2, is included on the board to provide a method to upconvert the Tx output signal. The AD8345 can be used in an image rejection architecture.

The Tx data bus data uses J1 and requires configuring depending on the configuration of the AD9861/AD9863.