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Results on Analog.com

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  1. Designing an AM/FM Active Antenna LNA Solution with the MAX2180 LNA
    Design Note
    Reference design for an automotive antenna features an AM/FM low-noise amplifier (LNA) for active antenna modules. Article details the capabilities, features, and ease of design with an AM/FM active antenna LNA.
  2. Designing a Low-Cost, Low-Component-Count GPS Receiver
    Design Note
    Describe the key system parameters that should be considered when designing a low cost, low component count unassisted commercial GPS receiver.
  3. Designing Output-Matching Networks for the MAX1472 ASK Transmitter
    Design Note
    This article illustrates an output-matching network and component values for the MAX1472, a crystal-referenced, phase-locked loop (PLL) transmitter that transmits OOK/ASK data in the 300MHz to 450MHz frequency range.
  4. Designing with the MAX2648 5GHz LNA for High-Frequency Stability
    Technical Articles
    Sep 27, 2002
    Optimize the RF input and output matching circuits on the MAX2648 LNA. A small stub insures stability.
  5. Design Considerations for Using the DS26504 Jitter Attenuator
    Design Note
    How to use the DS26504 Jitter Attenuator to avoid phase slip and wander.
  6. Design Note 1004: An Efficient and Low Cost Alternative to LEDs for Backlighting Handheld Computer Displays
    Design Note
    The backlight for a handheld computer’s liquid crystal display should be efficient, compact and inexpensive. The two primary competing backlight solutions, white LEDs and Cold Cathode Floresent Lamps (CCFLs), satisfy some of these requirements but neither excel in all.
  7. Designing an LED-Based Video-Display Board
    Technical Articles
    Apr 10, 2009
    The following application note describes Maxim's approach of how to incorporate the powerful features of the MAX6974 to realized an LED-based video display board.
  8. Designing to Protect MAX2140's Internal ESD Diode During Nonstandard Operation *
    Technical Articles
    Dec 23, 2005
    This application note will present the cause of the internal ESD diode failure for MAX2140. It will provide the design guides and the example of the case calculations.
  9. Designing a Digital Satellite Equipment Control (DiSEqC)-Compatible Phantom Antenna Power-Supply System
    Design Note
    This application note discusses a design for a phantom antenna power-supply system compatible with the Digital Satellite Equipment Control (DiSEqC) communication standard.
  10. Design Porting Considerations for the MAX2870
    Design Note
    This application note compares the MAX2870 and ADF4350 synthesizer/VCO \r\nregisters and loop filter design in detail.

Results on EngineerZone

179,670
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    1. Out of band rejection in AD9361

      Forum Thread
      Answered
      Design Support AD9361/AD9363/AD9364
      30 March, 2023
      … receiver chain including Filters. Scenario is that desigred signal is at 3500MHz with 5MHz bandwidth having -70dBm and undesigred signal at 3510MHz with 5MHz bandwidth having 0dBm. Will undesigred signal will affect the desigred signal? If it will not then upto what power level? Please help in it. Regards Anki
      hardwaread9361Wideband Transceiver ICno osRF Integrated Transceivers

    2. RE: Receiver selectivity

      Forum Reply
      Design Support AD9361/AD9363/AD9364
      24 July, 2023
      My signal bandwidth is 5MHz centered in f0 MHz. Interferer is f0+6 MHz. But its power is -10dBm and desigred is in -80dBm. Regards Anki

    3. Design advice for using ADR3650 to power a bridge sensor load cell data acquisition system and act as an ADC/DAC voltage reference...

      Forum Thread
      Answered
      Voltage References
      22 April, 2025
      … has some supply concerns. What can ADI say about availability of the chip? Related to #1, I don't see much in the way of design guides, blog posts etc. for the ADR3650 chip in terms of practical layout examples, etc. Any practical design layouts available from ADI besides what …
      amplifiershardwareInstrumentation AmplifiersSeries Voltage Referencesvoltage referencesADR3650

    4. Size of nBlockSize in Algorithm Designer

      Forum Thread
      Answered
      SigmaStudio for SHARC
      16 April, 2025
      About Block Processing in Algorithm Designer，I want to know what is the size of nBlockSize in structure SSBlockAlgo?What is it determined by and can I customize it?
      softwarealgorithm designer

    5. Request for Mechanical Design Guidance – Wearable Optical Sensor Integration

      Forum Thread
      Answered
      Other Products (EN)
      11 April, 2025
      We are designing a wearable health monitor in a watch form factor, featuring an optical sensor (LED + PD) and ECG electrodes. To address light leakage and ensure good skin contact, we're exploring two design options: 1. Flat-shaped cover glass – We are seeking guidance on the recommended height at …
      hardwareOptical AFEsOptical Sensing TechnologyMAX86176

    6. Design Files For DC2100B EVAL Board

      Forum Thread
      Answered
      Battery Management System
      08 April, 2025
      The design files for the DC2100 available as as ZIP download file on the AD website do not contain the file DC2100B-1.ASC file. I am using Altium Designer and I cannot import the PCB design file without the ASC file. Could you please provide that? https://www.pads …
      hardwareBattery Cell BalancersDC2100Bltc3300-1battery managementltc3300

    7. AD9361 Custom HDL Design

      Forum Thread
      Answered
      FPGA Reference Designs
      07 April, 2025
      … On the software side, I am using the no-os driver to initialize the ad9361 chip.As a starting point, I am using the reference design for the FMCOMMS3 and I am currently working on the transmit part. I removed the dma part of the design to directly attach a …
      hardwaread9361Wideband Transceiver ICRF Integrated Transceivers

    8. Using GNU Radio with AD9081+ZCU102 with reference designs?

      Forum Thread
      Answered
      FPGA Reference Designs
      04 April, 2025
      … Radio. Is that something we should expect to work out of the box, or are we going to need to adapt the existing hardware/software designs to connect those pieces? Also, one of the main goals for our project is to build something space-grade (rad hard). As of April …
      softwareAD9081High Speed A/D Converters >10 MSPSMixed-Signal Front Ends (MxFE)

    9. Refernce design

      Forum Thread
      Answered
      FPGA Reference Designs
      02 April, 2025
      I am user reference guide for ADR9361 reference design to check the output on iio.
      softwareADR9361

    10. HDL Reference Design

      Forum Thread
      Answered
      FPGA Reference Designs
      25 March, 2025
      Hi, How is the clock input on external port ref_clk related to the ADRV9009 sample rate? It appears that the axi_clkgen blocks divide ref_clk by 4 to drive the tx and rx processing chains? Thanks, Andy
      hardwareadrv9009Wideband Transceiver ICRF Integrated Transceivers