Wideband RF Signal Processing
The AD9144 is a quad, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.8 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM) from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a typical range of 13.9 mA to 27.0 mA. The AD9144 is available in an 88-lead LFCSP.
- Greater than 1 GHz, ultrawide complex signal bandwidth enables emerging wideband and multiband wireless applications.
- Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies.
- JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design.
- Fewer pins for data interface width with a serializer/deserializer (SERDES) JESD204B eight-lane interface.
- Programmable transmit enable function allows easy design balance between power consumption and wake-up time.
- Small package size with 12 mm × 12 mm footprint.
- Wireless communications
- 3G/4G W-CDMA base stations
- Wideband repeaters
- Software defined radios
- Wideband communications
- Local multipoint distribution service (LMDS) and multichannel multipoint distribution service (MMDS)
- Transmit diversity, multiple input/multiple output (MIMO)
- Automated test equipment
The AD9625 is a 12-bit monolithic sampling analog-to-digital converter (ADC) that operates at conversion rates of up to 2.6 giga samples per second (GSPS). This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/antijamming measures.
The analog input, clock, and SYSREF± signals are differential inputs. The JESD204B-based high speed serialized output is configurable in a variety of one-, two-, four-, six-, or eight-lane configurations. The product is specified over the industrial temperature range of −40°C to +85°C.
- High performance: exceptional SFDR in high sample rate applications, direct RF sampling, and on-chip reference.
- Flexible digital data output formats based on the JESD204B specification.
- Control path SPI interface port that supports various product features and functions, such as data formatting, gain, and offset calibration values.
- Spectrum analyzers
- Military communications
- High performance digital storage oscilloscopes
- Active jamming/antijamming
- Electronic surveillance and countermeasures
The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.
In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.
The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.
- Wide full power bandwidth supports IF sampling of signals up to 2 GHz.
- Buffered inputs with programmable input termination eases filter design and implementation.
- Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.
- Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.
- Programmable fast overrange detection.
- 9 mm × 9 mm, 64-lead LFCSP.
- Diversity multiband, multimode digital receivers
- 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
- General-purpose software radios
- Ultrawideband satellite receivers
- Signals intelligence (SIGINT)
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
The automatic gain control (AGC) circuit is useful in multiple applications such as amplitude stabilization of a synthesizer, controlling output power in a transmitter, or optimizing dynamic range in a receiver. The circuit shown in Figure 1 uses the ADL6010 detector, along with the HMC985A voltage variable attenuator (VVA) and the HMC635 RF amplifier, to provide automatic gain control over a wide range of input frequencies (20 GHz to 37.5 GHz) and amplitude. Circuit performance, as measured by the AGC figures of merit described in this circuit note, are very good between 20 GHz and 30 GHz. The overall gain of the circuit falls off above 30 GHz. However, improvements can be made over narrow bands by using matching techniques not explored in this circuit note.
The AGC circuit has applications in microwave instrumentation and radar-based measurement systems.
Aerospace and Defense
- Electronic Surveillance and Countermeasures
- Military Communications
- Aerospace and Defense Radar
The circuit shown in Figure 1 is an RF power measurement circuit that accurately measures the power from an RF signal source within a frequency range of 9 kHz to 6 GHz, and has a nominal input power range of 45 dBm (−30 dBm to +15 dBm).
This circuit constitutes a complete rms RF power meter in a tiny form factor that can be powered entirely from a 5 V USB power supply. The measurement signal chain consists of an rms responding RF power detector and a 12-bit, precision analog-to-digital converter (ADC). These devices are powered by a CMOS linear regulator which generates 3.3 V from the 5 V USB supply.
A simple calibration routine can be performed at multiple frequencies to compensate for any frequency response variation of the circuit. Calibration data is stored in a lookup table, which is referenced during the RF power measurement.
The circuit shown in Figure 1 is a broadband low distortion RF transmitter with a dual high speed TxDAC+ digital-to-analog converter (DAC), a wideband I/Q modulator, and an output driver amplifier.
The devices are well matched, and the direct interface between the DAC and the modulator, and between the modulator and the driver amplifier, offers a compact solution for many RF communications applications including 3G, 4G, and LTE.
The circuit block diagram shown in Figure 1 is a low phase noise translation loop synthesizer (also known as an offset loop). This circuit translates the lower 100 MHz reference frequency of the ADF4002 phase locked loop (PLL) up to a higher frequency range of 5.0 GHz to 5.4 GHz, as determined by the frequency of the local oscillator (LO).
The translation loop synthesizer has very low phase noise (<50 fs) in contrast to a synthesizer using only a PLL. The low phase noise is because of the very low N value used by the ADF4002 integer-N PLL, which controls the voltage controlled oscillator (VCO). In this example, the ADF4002 phase frequency detector (PFD) runs at 100 MHz, and N = 1, yielding phase noise performance that is not limited by the N value of the PLL.
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The circuit shown in Figure 1 accurately measures return loss in a wireless transmitter from 1 GHz to 28 GHz without any need for system calibration.
The design is implemented on a single circuit board using a nonreflective RF switch; a microwave RF detector; and a 12-bit, precision analog-to-digital converter (ADC). To evaluate the circuit over the widest possible frequency range, a dual-port directional coupler with SMA connectors was used instead of a narrow-band, surface-mount directional coupler.
The circuit measures return loss of up to 20 dB over an input power range of 25 dB (return losses in excess of 20 dB can be measured over a smaller input power range).
A unique feature of the circuit is that it calculates return loss using a simple ratio of the digitized voltages from the RF detector, thereby eliminating the need for system calibration.
The circuit shown in Figure 1 uses RF MEMS switches to route an RF signal between two surface-mount RF attenuators and two straight through paths.
Attenuating RF signals is commonly done in RF test instrumentation and receiver front ends to protect downstream circuitry and to increase dynamic range. Using discrete attenuators and switches maximizes design flexibility and routing options. In the Figure 1 circuit, two ADGM1304 single-pole, four-throw (SP4T) RF MEMS switches in a back to back configuration yield four independently switchable paths between input and output. Two of the paths are straight through transmission lines, the third path contains a 6 dB attenuator, and the forth path contains a 9 dB attenuator. Key to realizing this application is the use of ultralow insertion loss and highly linear switches to multiplex between the different path options.
The switches must be as transparent as possible to the RF signal and add as little insertion loss and distortion as possible. The ADGM1304 switches offer best in class insertion loss of 0.26 dB typical at 2.5 GHz, and a third-order intercept (IP3) performance of 69 dBm typical. In addition to insertion loss and distortion, another key benefit that the MEMS switch brings to this application is its ability to operate down to true dc. This means the switches do not limit lower frequency operation in a typical RF instrumentation attenuator switching application, and enables the instrument to pass dc bias voltages when required.
The physical size of the ADGM1304 device at 4 mm × 5 mm × 0.95 mm yields a significant reduction in printed circuit board (PCB) area compared to traditional electromechanical relays switching solutions. In addition, the actuation speed of the ADGM1304 switch is 30 μs, a significant improvement over electromechanical relays, which are in the order of milliseconds and introduce significant time lag in measurement systems. The actuation lifetime of the ADGM1304 device is guaranteed for one billion cycles, which is a major improvement over electromechanical relays and significantly increases overall system reliability.
- AN-2061: Wideband Bias Tee Design Using 0402, SMD Components
- AN-1353: How to Bypass VCO Calibration for the ADF4355-2, ADF4355, ADF4355-3, ADF4356, ADF5355, and ADF5356 (Rev. D) PDF
- AN-1396: How to Predict the Frequency and Magnitude of the Primary Phase Truncation Spur in the Output Spectrum of a Direct Digital Synthesizer (DDS) (Rev. 0) PDF
- AN-1390: Manual Band Selection for PLL Lock Time Reduction (Rev. 0) PDF
- AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) PDF