### Abstract

A compact, accurate, sub-1V, low-impedance, low-dropout bandgap reference is presented in this paper. The circuit concept presented here is a sub-1V (0.9V in the design example) bandgap reference that can be set from a bit above V_{BE}, depending on the operating temperature range, and up to the normal bandgap voltage. The circuit idea is realized in 90nm BiCMOS technology. Simulation results show that over a 200°C temperature range, the proposed circuit can achieve 15ppm over line and load regulation. The core can be realized in a CMOS process using parasitic pnp devices.

A similar version of this article appeared March 10, 2014 in ELETimes.

### Introduction

A voltage reference is a critical building block in most analog circuits. In battery-operated, portable applications the minimum system voltage is continuously being lowered to prolong battery life. The theoretical minimum supply needed for analog circuitry is a threshold plus the saturation voltage of a current source, usually V_{DSSAT}. For BiCMOS processes, or CMOS processes with parasitic pnp transistors, the minimum operating voltage will be V_{BE} + V_{DSSAT}, assuming that the CMOS VT threshold is lower than V_{BE}.

In this article a new bandgap reference core is presented that can be set anywhere between slightly above V_{BE} to V_{BG}. The lowest output voltage (V_{0}) depends on the lowest temperature that needs to be covered. The design examples below will show that these configurations approach the theoretical minimum operating voltage by 50mV to 100mV from -50°C to +150°C.

Sub-1V voltage references have been realized in different ways before. Engineers have documented^{1–5} various architectures in current mode, where CTAT and PTAT currents are generated and added together to a resistor to generate a reference voltage. However, it was shown^{6} that those configurations have high noise due to the current mirrors. Because of the mirror mismatches, it is difficult to get the same accuracy using current mirrors compared to the normal bandgap configuration. Without trimming, a well-designed bandgap circuit can normally achieve 3% to 5% 6δ accuracy from -40°C to +125°C. Even with a reasonably high overdrive, it is difficult for the current mirrors to achieve this level of accuracy. If overdrive is increased for better matching, it also increases the necessary headroom as V_{DSSAT} is increased.

There is another way^{6, 7} to generate a sub-1V reference. The reference voltage is expressed in Equation 1:

V_{REF} = kV_{BE} + ΔV_{BE} = kV_{BE} + V_{T}ln(N)

where N is the ratio of the area of the two emitters.

As shown in Equation 1, the voltage is set in the 100mV to 200mV range. A presentation in 2006^{7} gave the design example as N = 10, V_{REF} = 130mV.

A reference voltage close to ground is not desirable because the noise and the offset in the next stage will be proportionally larger than the reference voltage. Consequently, the overall accuracy deteriorates. This article presents a novel approach that resolves the aforementioned issues and provides superior performance. For example, a 0.9V reference can be generated with a 1.0V supply or lower, depending on the load.

### The New Proposed Core for a Sub-1V Reference

#### A BiCMOS Process with npns

Figure 1 shows the proposed core.

Mathematically, it can be shown that V_{0} becomes a scaled version of the bandgap voltage, V_{BG}:

I_{2} × R_{2} = ΔV_{BE} = V_{T}ln(N)

V_{0} = (1 - R_{1}/R_{3}) × V_{BG}

where:

V_{BG} = (V_{BG1} + V_{T} × lnN × R_{3}/R_{2} × ((R_{1} + R_{2})/(R_{3} - R_{1}))

The supply headroom requirement is V_{0} + V_{DSSAT}, and the output is low impedance.

#### A CMOS Process with Parasitic pnps

A possible pnp version is shown in Figure 2.

### Design Example with Simulation Results

A simplified version of Figure 1 is shown in Figure 3; it saves an op amp (X2). The I_{3} current can be generated by adding two resistors along with Q_{3}. In this case, I_{4} can be set to I_{0} at room temperature by choosing an appropriate R4, approximately equal to R_{1}/2. At other temperatures, I_{4} will not be equal to I0, and this will introduce an error term. But since V_{BE} is a very weak function of I_{0}, therefore, the error is negligible. See Figure 4.

As a design example for this core, V_{0} = 0.9V is chosen.

For low-power applications, the quiescent current (I_{Q}) is targeted in the µA range. Based on the configuration in Figure 3, we have three variables, R_{1}, R_{2}, and R_{3}, and two equations, (Equation 3 and Equation 4), defined by V_{0} and V_{BG}. Therefore, I2 is chosen to get one more equation to derive all three resistor values.

From Equation 3:

R_{2} = (V_{T} × lnN)/I_{2}

From Equations 4 and 5:

There is no individual knob to control the output voltage and its TC separately. Here is the procedure to fine-tune the circuit to the zero TC point and to obtain the desired output voltage.

- Find the exact V
_{BE1}voltage in simulation. - Find V
_{BG}by adjusting R_{2}until V_{0}is zero TC. Now follow this procedure: increase R_{2}if V_{0}has a positive TC; decrease R_{2}if V_{0}has a negative TC. Note the value of zero TC V_{0}, then:

V_{BG}= V_{0}/(1 - R_{1}/R_{3}) - Recalculate R1, R2, and R3 using the new V
_{BG}and V_{BE}values.

V_{BG}= 1.203V

V_{BE1}= 0.58V

I_{2}= 1.0µA

N = 8

R_{4}= ½R_{1}= 206kΩ.

The final calculated design parameters are shown in Table 1:

°C | -55 | 25 | 150 |

V_{BE1} |
0.74 | 0.58 | 0.33 |

V_{BG} |
1.203 | 1.203 | 1.203 |

V_{T} |
0.019 | 0.026 | 0.036906 |

I_{2} |
7.32E-07 | 1.00E-06 | 1.42E-06 |

I_{3} |
4.52E-07 | 3.55E-07 | 2.02E-07 |

I_{0} |
2.79E-07 | 6.45E-07 | 1.22E-06 |

I_{1} |
2.79E-07 | 6.45E-07 | 1.22E-06 |

R_{1} |
4.120E+05 | 4.120E+05 | 4.120E+05 |

R_{2} |
5.407E+04 | 5.407E+04 | 5.407E+04 |

R_{3}R _{4} |
1.636E+06 2.060E+05 |
1.636E+06 2.060E+05 |
1.636E+06 2.060E+05 |

Realizing Figure 3 in a 90nm BiCMOS process with transistor circuitry, the simulation results are plotted in Figure 4. The typical case is: supply voltage = 1.5V; output load = 10µA; all process corners (bipolar, CMOS, resistor, capacitor) having line and load combinations with supply voltage = (V_{0} + 0.1V) and 1.65V; output load = 0µA and 20µA. The circuit has temperature compensation and 0.1% LSB trim. The results show that V_{0} stays within 2.6mV, less than ±0.15% from -50°C to +150°C, or 15ppm over line and load. With processes variation and 0.1% LSB trimming, this bandgap voltage reference can achieve ±0.45% accuracy over 200°C temperature range.

### Performance Comparison

Table 2 compares the performance of proposed cores with existing designs:

Proposed Core | Reference 5 | Reference 3 | Reference 6 | |
---|---|---|---|---|

Tech/m | 90n BiCMOS |
500n CMOS |
600n CMOS |
500n BiCMOS |

V_{DD}/V |
1-1.65* | 0.93-5 | 0.98-1.5 | 1 up |

V_{REF}/mV |
900 | 228 | 603 | 190.9 |

TC/ppm | 15 | 34 | 34.7 | 11 |

I_{Q}/µA |
6 | 28 | 18 | 20 |

PSRR/dB @100Hz @10kHz @1MHz |
-84 -62.2 -28.6 |
-58 – -12 |
– -44 – |
– |

Noise/(nV/√Hz) @100Hz | 1573 | 200 | – | 40 |

Area/mm^{2} |
0.023** | 0.0464 | 0.24 | 0.4 |

*It uses 1.65V devices, so the maximum voltage is 1.65V. If a 4.5V device is used, it can go up to 4.5V. **Die size is based on placement of all components in corresponding wells with DRC cleaned. |

### Conclusion

This article shows an elegant way of creating a compact, sub-1V bandgap reference in a low-dropout and low-impedance configuration. This proposed solution has a superior accuracy of about 20ppm with load, line regulation, and temperature variation. The headroom requirement approaches the theoretical minimum. The die size is comparable with a traditional bandgap reference with three more components (2 resistors and 1 npn). This design is small and can enhance the circuitry working with a lower battery voltage that is beneficial, even critical to portable designs.

### 参考电路

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^{2} P. Malcovati et al., “Curvature compensated BiCMOS bandgap with 1-V supply voltage,” **I***EEE J. Sopd-State Circuits*, vol. 36, no. 7, pp. 1076-1081, Jul 2001.

^{3} K.N. Leung and Phipp K. T. Mok, “A sub-1-V 15ppm/C CMOS bandgap voltage reference without requiring low threshold voltage device,” *IEEE J. Sopd-State Circuits*, vol. 37, no. 4 pp. 526-530, Apr, 2002.

^{4} Zhidong pu and Yuhua Cheng, “A Sub-1V CMOS Bandgap Reference with High-order Curvature Compensation,” *IEEE International Conference of Electron Devices and Sopd-State Circuits*, 2009 EDSSC.

^{5} David C. W. Ng, David K. K. Kwong, and Ngai Wong, “A sub-1V, 26uW, low-output-impedance CMOS Bandgap Reference with a low Dropout or Source Follower Mode,” *IEEE Transactions on VLSI Systems*, Vol. 19, No. 7 July 2011.

^{6} Keith Sanborn, Dongsheng Ma, and Vadim Ivanov, “A sub-1-V Low-Noise Bandgap Voltage Reference,” *IEEE Journal of Sopd-State Circuits*, vol. 42, no. 11, November 2007.

^{7} I.M. Filanovsky, V. Ivanov, K.E. Sanborn, University of Alberta, Edmonton, Canada, Texas Instruments, “Sub-1V Supply Bandgap voltage references based on Asymmetric Differential Pair,” *49th IEEE International Midwest Symposium on Circuits and Systems* (MWSCAS), Vol. 2, 2006.

G. Giustopsi, G. Palumbo, M. Criscione, and F. Cutri, “A low-voltage low-power voltage reference based on subthreshold MOSFETs,” *IEEE Journal of Sopd-State Circuits*, Vol. 38, No. 1, pp. 151-154 January 2003.

Giuseppe De Vita and Giuseppe Iannaccone, “A sub1V, 10ppm/C, Nanopower Voltage Reference Generator,” *IEEE Journal of Sopd-State Circuits*, Vol. 42. No 7, pp. 1536-1542, July 2007.