A Driver for Imaging (Short Version)

The circuit shown below works great. You should try it.

 

 

This is intended for nominally 0-3V single ended or differential signals, from CCDs, CMOS image sensors, or other similar signal sources. As shown, SNR is 88dB. With the AD8008, in place of U1, and a few other minor changes, it produces 92dB SNR, settles to 0.02% in one pixel at 15Msps. See the long version of this article for more detail. Low noise, and stable bias may be required at in- to optimize use of the input range.

A Driver for Imaging (Long Version)

Let me begin by stating that this driver is not necessarily just for imaging applications. By imaging, we actually mean: any signals that involve sample-synchronous steps to distinct levels, such as you may see from a CCD. Or more precisely, abrupt steps, or transients followed by a relatively static dwell at an arbitrary voltage level, preferably involving some reasonable portion of the clock period to settle before sampling. These distinct levels may be pixels. This can mean, for example, CCD field or linear array sensors, optical, X-ray or infrared image sensors, or in fact, multiplexed signals. In the event that this driver is preceded by multiplexers, spectral power distribution of the signals selected by the multiplexer should be preponderantly below 1 MHz, at least in the period some 10-15 nsec prior to sampling.

If this use used for CDS sampling, the actual maximum pixel rate would be 7.5Msps, and the black reference must be subtracted in the digital domain.

 

 

The LTC2387 is an 18 bit ADC, with SNR and linearity well beyond that of integrated CCD solutions.

The dynamic range may be used instead of a PGA to accommodate a large range of integration times, or different devices. Needless to say, this is not targeted at consumer imaging applications. The original intent of this article was to use the LT1396, for both U1 and U2, but lower noise can be achieved with a number of current feedback amplifiers from ADI. The benefit of the higher SNR, at the cost of higher power consumption, may be limited by the characteristics of the sensor, and to some extent on the use of the sensor. For example, If multiple frames can be averaged, and resolution is otherwise compromised by pixel to pixel gain and offset variation, and noise, the higher SNR of the driver will be of limited value in any case.

This circuit was tested with the AD8008, and AD8002 several months prior to the time of writing. At the time, this other population was not intended to be published. It was done for investigative purposes only. Current feedback amplifiers (CFAs) from other vendors have also been tried, as they have been in part I, and part III of this series. But only one vendor’s parts produced meaningful improvement over the LT1396. Now, it seems appropriate to release it, as that vendor is now us. The AD8008 also has lower in+ bias current than the LT1396.

This topology is related to the July 2013 article “Near noiseless ADC drivers for imaging”. That version was published for the 84dB SNR 20Msps LTC2270, with its 2.1V p-p input range. I would suggest reading that article as well if more detail is desired.

 

 

The difference between this present circuit and the year 2013 topology for the 20 Msps LTC2270 is that this new version must provide gain, in the input stage, to achieve adequate signal swing for the 8V peak-peak input range of the LTC2387. This approach assumes that the “video” signal is in the commonly encountered 3-5V peak to peak range. The signal level at the outputs of the first stage must be greater than the input range of the ADC as it is attenuated in a common mode servo stage prior to the ADC. The common mode servo provides essentially noiseless single ended to differential translation. The attenuation in this version is only 3.8dB, less than in earlier cases where I have used this approach. This is in part because the undistorted signal swing at the output of the driven input amplifier is limited to about 8V peak to peak on a 12V supply. The driven amplifier, ant this gain, and assuming single ended drive, has to deliver almost twice the excursion of the complement amplifier. If driven with a nominally balanced differential signal, and this version differs from the original article in that it is essentially differential, the input stage gain could be higher, and SNR would then improve. This improvement would be partly due to the in- noise current becoming less significant at higher gain, and partly due to greater attenuation in the common mode servo, reducing the effects of both noise voltage and noise current. The suppression of the common mode translates single ended drive, or in this case, rather poorly balanced differential drive, to decent differential drive, rather like a transmission line balun. The original article used the LT1395 family as a unity gain input buffer, taking the power output, the actual power used to drive the ADC, directly from the inverting input, as if it were an emitter follower. The LTC2387 could possibly be driven in precisely this fashion with this board, if the video signal were 10V peak to peak differential. It would require somewhat different population. Of course, 8Vp-p differential drive from a sensor could possibly drive the ADC directly, if the common mode were correct, and if it were to have well controlled output impedance. The LTC2270 version translated 4-5Vp-p single ended video input to 2.1Vpk-pk differential. The LT1396 was performing essentially as a pair of complementary emitter followers within a feedback loop. The output of the amplifier was only used to close the loop, via the minimum 402Ω FB resistor.

The LT1395 used in that fashion, is quite low noise, and very fast settling. In producing gain however, its 4.5 nV/√Hz input noise voltage, and the inverting input noise current of 25 pA/√Hz are the dominant noise sources. Unfortunately, lower noise voltage feedback amplifiers, and rail-rail output amplifiers, often promoted as suitable for imaging drivers, are generally too slow.

Pattern Noise and Settling

Slow settling will translate any timing variation, any clock feed through subject to deterministic variation in propagation delay or amplitude, any crosstalk, into what is commonly referred to as “pattern noise”. This is often in the form of diagonal lines, sometimes with other interesting but nevertheless unwanted effects. The patterns often give clues as to the origin of that variation. A repetitive variation in clock feed-through, or charge injection in the CCD will produce similar effects to timing variation if settling is not complete. The same situation would exist in multiplexed signals with variation in timing, or with variable charge injection related to the devices in the topology, or the commonly encountered “charge sharing” in the output capacitance of multiplexers. Horrific timing variation may originate in software, in interrupt driven processors, and to a lesser degree in integrated timing engines, and in DLLs and other devices in FPGAs, rather than the sensor itself. Pattern noise can also originate in crosstalk mechanisms rooted in poor PCB layout design, and of course in power supply design as well, although often indirectly, translating ripple to variation in charge injection.

There have been cases where it was asserted by imaging customers that slow settling should not be an issue, because it was believed that there were no disturbances between the pixels and no timing variation. In retrospect these seemed often to be those cases where pattern noise was later found to be a problem. In some cases however, the pattern noise was undoubtedly the result of ringing of a poorly chosen differential amplifier unsuited to low gain, high slew applications. Ringing, due to poor phase margin, can also translate timing variation into pattern noise as it is another form of memory. A complex reactive load reflecting back into the output of an amplifier can produce pattern noise as it may not just delay, but may prevent settling, in a fashion that is subtle, not very apparent looking at the settling behavior on a scope or in data sheets, or in simulation. We have had people send simplistic models questioning why the simulation does not show the effects.

An amplifier that does not settle adequately will may appear to have poor PSRR, as the power supply will have some effect on slewing and settling. This can be misinterpreted as being simply a power supply issue, or a PSRR issue. Fixing the power supply would be like putting a band aid on a severed leg.

Many amplifiers have asymmetrical slewing, which, combined with a high dv/dt signal source, and slow settling, or even post filtering, may translate clock feed-through variation, charge injection, and other inter-pixel disturbances into discernable artifacts in a flat field. In many cases, it is advisable to have some band limiting before such an amplifier, even though one might expect it to exacerbate the slow settling. This issue could be labeled as envelope detection. RFI-like artifacts conducted from the imaging device into a slow settling amplifier can produce patterns, as can reception of cell phone traffic, although that is more random. A consistent settling time, although perhaps not quite fast enough, without approaching the non-linear effects of slew rate limiting, would be easier to correct in software, assuming a model of the simple settling behavior can be implemented in the digital domain.

At the root of some of these pattern noise problems is the fact that the settling time that is available to the amplifier is often less than anticipated, and often less than 50% of a pixel interval. At 15Msps, this means only 33 nsec. As an example, the LT6237, sometimes unwisely promoted for imaging, will need about 1 usec to settle to 18 bits, in a 4Vp-p scenario. This is arguably too slow by a factor of about 30. Of course, the appropriate amplifier must also be low noise.

At 15 Msps, and approaching 18 bits, this appears to leave CFA’s as the only apparent choice. The LT1396 settles to 0.1% in 25 nsec, and is not characterized in the data sheet beyond this. In any case, this is not quite good enough in terms of settling, nor in terms of noise. The settling time of the AD8008, to 0.1%, is 18 nsec (2Vp-p), and the AD8002, is 16 nsec. Note that I am only using settling to 0.1% for comparison purposes, and yet settling to even 0.01% is arguably not adequate. Of course, many imaging devices no not warrant an 18 bit convertor, however, if multiple frames can be averaged, the benefit of 18 bits may be realized statistically.

The circuit as shown above settles to within 0.02% in one pixel interval, after a full scale step, at 15Msps, and within 0.01% at 10Msps.

SNR

The settling of the amplifier is not however, the only factor in choosing an amplifier. Inverting input noise current is dominant in low gain (<7dB) applications of all these CFAs.

The LT1395 family with 4.5 nV/√Hz, and 400 MHz GBWP, has often been my workhorse. In the circuit below, with LT1396 as U1, we see SNR of 87.5dB. This is 4dB better than the 83.5dB of the previous LTC2270 version as published. It is not however better in terms of noise density at the input of the ADC; as it is the 12 dB increase in input range that is responsible for the increase in SNR.

However, using the AD8008, we see 90.7dB SNR; and with the AD8002, SNR of 91.5dB. There is some trade-off between settling and SNR. Versions with faster settling are worse in terms of SNR by about 1 dB.

Thermal Tails

CFAs exhibit thermal tails that are due to localized heating, primarily of the 2nd transistors in the input stage, that manifests itself most severely during the time before this heating has a chance to reach their counterparts in the 1st transistors. If all 4 input transistors were at the same temperature, their VBEs would largely cancel out. They are not, however, at the same temperature.

The magnitude of the effect is most severe, on the order of 0.05%, when there is an extended dwell at the opposite end of the transfer function. One apparent thermal time constant is on the order of 1.3-1.5 usec, however it is not a simple time constant. There is a time lag between counterpart transistors, the thermal time constant of the transistors seeing the dissipation, and the thermal mass of the chip itself. The use of a mercury wetted relay brought this to light, but limits the duration of pulses that can be produced. This imaging driver/ADC combination also brought to light effects that I had not observed in mercury wetted switches. The behavior at onset and cessation of electrical conductivity shows evidence of physical phenomena involving surface tension. The use of analog switches for test signal generation however was hiding these effect from us in early stages, seemingly due to long carrier lifetimes delaying complete turn-off, and thereby producing extended settling, oddly enough, an error of the same order, but opposite polarity to the thermal effect, and with duration of about 750 nsec to 1 usec. On a happier note, for short duration transients, between pixels, the thermal error on returning to the original state is minimal. With clock feed-through, or other transients between pixels, in a flat field, these effects should not produce pattern noise, as slow electrical settling would.

As pulse duration, and signal levels are varied, the effect varies from seemingly over-damped slow settling, to immediate overshoot. The overshoot is not of that type associated with poor phase margin in a feedback loop, or ringing, but appears as a simple tau of 1.3-1.5 usec. However, as there are opposing effects with different tau, the shape of the settling is variable with timing, producing in some scenarios, an illusion of fast settling, only to be followed by a delayed overshoot. For many imaging applications, this thermal tail should be a non-issue as it is likely to be seen only at the beginning of a line, or frame. For medical imaging, where fast settling in response to short duration transients, in a flat field, is most important, the thermal tails, that would appear as subtle ghosting in a hypothetical high contrast image would be imperceptible in a low contrast field, even when enhanced to high contrast. Were it possible to display a high contrast color image of this resolution, it would require on the order of 8 billion colors to make the thermal tail discernible.

Analog or Digital Correction?

There is a first order compensation network, that I did not make provision for on the PCB, that consists of 0.75 pF, in series with 68KΩ, placed across R28. This was tested in the form of 1.5pF-68K-1.5pF.

This has a tau of 51 nsec. Although the actual thermal tail is a more complex function, associated with a complex 3D thermal environment, and thermal lag associated with heating the neighboring input transistors, at which point there is some degree of cancelation, the simple network does a decent of hastening settling in cases where the disturbance in short, in less than 1 clock cycle. However, if settling to 16-18 bit levels is required after a variable duration excursion to the opposite extreme of the input range, modeling of the thermal processes in the amplifier, in the digital domain, may be the best way of dealing with this issue. It may be necessary to employ software learning as there are likely multiple contributors, including the imaging device, which may confound a simplistic approach.

Linearity

The testing of the linearity of this circuit, done in a fashion similar to the original article, involved a high level square wave at fs/2, or fs/4, combined with a lower amplitude sinusoid, the square-wave at Nyquist emulating pixels. If the timing of the sampling, relative to the square wave, is pushed towards the end of the “pixel”, as such, where you would strive to sample an actual pixel, the inter-modulation distortion should be at a minimum. Sampling earlier is not advisable as this would provide less settling time. Less obvious is that if sampled too early, the common mode servo will not have time to settle, and hence, will not effectively suppress common mode. Some people have questioned the need for high linearity in an imaging application, but I will not address that even though I could. The linearity of the LT1396 version is not as good as the AD8008, likely related to crossover distortion in the LT1396. However, the linearity of the LT1396 version may not in fact be a concern for many imaging applications, and the 87dB SNR may be acceptable, as it is likely to be dominated by the sensor. In this case, the lower current consumption of the LT1396 may be attractive. The AD8002 has somewhat more distortion than the AD8008 version, but lower noise, so it may be preferable for other customers. Many imaging devices will dominate even the –87dBfs noise floor of the LT1396 version by 20 dB, or thereabouts. With short aperture times, low illumination, low dosage excitation, or small area imagers, the SNR of the driver will not matter… much. In fact, the LT6411, a device derived from the LT1395 family, and still on a 12V process, has considerably faster settling time, due to internal feedback resistors, and yet, should produce about the same noise floor as the LT1396 version, and was under consideration for a new iteration of the above board. There was a 2nd variant built for the AD8003 triple, but it proved to have more severe thermal tails, although it may yet have some merit, as it is faster.

The present circuit differs from the original 2013 imaging topology for the LTC2270 in that the input stage also contributes to the translation from single ended signaling to differential. As it has a differential gain of approximately 3, the output from the first stage has a common mode component that is reduced relative to the differential component, by about 14 dB. As such, the output common mode servo could remain much the same as the original design even though the input range of the ADC is 4X higher. This higher gain, higher input range version does however, have an additional common mode loop that controls level shift, and reduces the output servo’s role in level shift. This level shift however may need some involvement on the part of a microcontroller and a DAC. The prototype had a high gain in the servo, and in the case of dramatic changes in illumination, the servo would have to respond. Reduced gain in that servo may be necessary. (C11 paralleled with a resistor). It is a question of the video level, as 0-4V or 0-5V do not allow as much headroom. The level shift may be simply a fixed bias if input common mode is relatively stable.

The common mode output servo must control a pair of nodes, that in common mode, must not appear as capacitive reactance. The output filters isolate the common mode servo from both the output of the first stage, the level shift servo, and the input capacitance of the ADC, as well as various transmission lines. The filter also reduces aliased noise bandwidth as much as possible, as well as reducing the frequency content of the transients returned from the ADC, and from transient common mode from the front end, neither of which the common mode servo could handle well, allowing it to remain in closed loop operation.

The common mode servo in this LTC2387 version, U2A operates into the output filter, via C5 and C6, and part of the network intended to appear as absorptive to the ADC. Without this feature, following the servo with a diplexer stage may compromise common mode settling. The circuit board has provision to move the last absorber from R13 to R30, for example, or split between the two. However, returning the entire common mode transient power to the output of the common mode servo is likely unwise. The servo could be regarded as reducing common mode impedance without affecting differential impedance.

L1, L2, L3 and L4, are an integral part of the common mode loop, isolating the controlled node(s) from capacitive loads C9, and C4. The output end of the filter L4 and C4, and counterparts, are differential diplexers that appear absorptive to the ADC at higher frequencies. Differential signals, do not interact with the common mode servo, but common mode components will see low impedance at the node between L1 and L4, and its counterpart.

Much as explained in part III of this series, loose tolerance of components in the output servo can compromise SNR and distortion. Rather than repeating details explained in the original article, I would ask that you read those if this article appears a bit short on details.

The use of CFAs with their relatively high input current could potentially be a source of problems for some sensors. The maximum in+ current for the LT1395 is 30 uA. However, many lower noise VFB amplifiers also have quite high input current. The LT6200, for example, has a max bias current spec of –40uA, and the LT6237 has a 12uA input current spec, and yet both are too slow. The AD8008 and the AD8002, have 8uA, and 10uA max input+ current respectively. The use of the LTC6268 FET amplifier (5 nV/√Hz) as the input stage could be entertained if sample rates are less than 10 Msps. However, the LTC6268 is limited to a 5V supply, so a differential video signal would be required to be practical.

Testing and Validation

As there was no budget to acquire, or time to devise an 18-bit-linear CCD emulator, nor likely any CCD or light source, for that matter, that is likely to provide us any way of proving that this solution is linear to the extent that we would like to believe, we have no choice but to clarify the case that was made in the original article, and refine it. We did receive comments that imaging customers did not know how to interpret the case we had presented.

 

 

The test case in the original article was a square wave at Nyquist, combined with a 70 KHz tone. In the presence of the square wave, there were some IM products produced, but no change in the apparent power of the fundamental, at least not out to 3 decimal points. The level of IM distortion in the sinusoid was quite low, in the 15-16 bit level, with the AD8008.

In the present design, using the LT1396, the spur at Nyquist-fin, was at about –65dBfs, or about –45dB relative to the –20dB sinusoid. With the AD8008, it was at –98dBfs. That is the same as the power in the quantization error of a 16 bit ADC. I am not saying it originates in the quantization error; it is just comparable in terms of power. In a time domain application, dominated by thermal noise, it is then irrelevant, at least in the case of the AD8008.

In this new case, the source of our single ended square wave is an ADG772 analog switch switching between two reference voltages, each with source termination for the transmission lines. They are not end terminated at the amplifier other than at high frequency, in R18. This switch is differential, and the unused lines are also source terminated. Note that L4, in parallel with R18, reduces the source impedance, to improve noise density. R40 and R44 are not termination as such, and the value is dependent on the imaging device. Unbuffered imaging devices may require that these resistors be absent. Repetitive charge transfer represents a fairly low impedance, and will provide adequate bias current.

If driven single ended, the other input can be biased with a source that emulates the impedance of the imaging device, or alternatively with a low impedance from a low noise voltage reference.

The input current of CFAs is high relative to many voltage feedback amplifiers, and if the only storage mechanism were C16, it could droop nearly 20mV during one clock cycle at 15 Msps. If timing is deterministic, this is simply an offset. If timing is variable, this could become noise, or patterns. Droop of 20 mV in a 4V range is 0.5%, or 1300 counts in an 18 bit convertor. If, you were to have 50 psec total jitter between timing signal and sampling, it would translate to about 1 lsb of noise. Now, 50 psec is a lot of jitter by high speed standards, and 1 lsb is 20 dB below the thermal noise, so it is not likely to be a source of noise unless timing were software driven. Higher priority Interrupts in software could produce very significant compromise. Note that DLLs in FPGAs can easily have 50 psec jitter.

In this LTC2387 version of the inter-modulation tests, we have increased the AC frequency to 300 KHz, for reasons related to generators, filters, and DC blocks, but dropped its power level to –20dBfs, such that the square wave drive has near full amplitude. IM products are typically maximal when power is equal in the two tones, but the higher amplitude transient is closer to actual imaging signals. This scenario is intended to emulate near full scale steps in an imaging signal, but using the modulation of the weaker sinusoid as a measure of the linearity. If there were significant non-linearity, either in the form of compression, or in the form of differential phase error, the 3rd order inter-modulation products would manifest themselves offset by 300 KHz from the square wave. If there were compression, the amplitude of the fundamental would also change, although a significant number of digits would be required to see the effect. We added digits to fundamental power Pscope, in order to test this.

The symmetrical, bimodal nature of the signal resulting from a sinusoid superimposed on two distinct logic states, for want of a better term, symmetrical about bipolar zero, would perhaps not produce significant 3rd order IM if there were the same degree of compression (reduction of gain) in those two states. It would produce products at 2fsine below Nyquist, resulting from alternation of the phase of the between those two states. So we also tested the combination of 300 KHz sine wave with a square wave, at Nyquist, toggling between bipolar zero and near either maximum of the transfer function. Compression near full scale would produce AM, which would appear as a tone at Nyquist minus f, outwardly the lower sideband, but in fact both sidebands combined as the upper sideband aliases on top of the other. This scenario did not in fact produce more severe 3rd order inter-modulation distortion, so linearity is presumed to be acceptable. Note that a slight offset from fs/2 in the square wave isolates the two sidebands, but also results in sampling throughout the entire “pixel”.

 

 

Figure 4 shows a square wave near Nyquist/2, not the two tone test with a square wave at Nyquist. The Harmonics indicated on the frequency domain plot are only the even order, with all the odd order components present in a square wave under fs. Asymmetrical slew rates would produce 2nd (in this case near Nyquist) , 4th (near DC) and above , This is shown only to clarify the test scenario. The asymmetry in slew rates is visible as the lines do not cross half way between the two states. If the square wave were at Nyquist, sampled prior to the changes of state, the data would be composed of pairs of samples of the same value. There would be no information on slewing, or settling. There are two time domain plots, with the upper plot exaggerated by a factor of about 125. The upper plot shows the overlapping nature of this scenario in a plot composed of dots, zoomed on the region near bipolar zero.

Criticism and Defense of Complexity

The most vehement criticism of this circuit, and other circuits in this series, is that of complexity. There are several basic truths that impose this level of complexity. High linearity requires high GBWP of the amplifiers, which unfortunately means a great deal of noise BW. The input BW of the ADC is 200MHz, or 27 Nyquist zones at 15Msps. If sampling were subject to this entire BW from the amplifier, assuming noise density is flat, the noise from the amplifier would be 14.3 dB* greater than if it were limited to 1 Nyquist zone. *(10log(200/7.5)=14.3 dB) As the amplifier dominates, that would be nearly a 14 dB penalty. This means the output must be filtered to get the benefit of the high SNR. However, you cannot limit the BW to 1 Nyquist zone and get fast settling. Some 3-5x the Nyquist BW is required. There is still a 7 dB benefit in limiting the BW from the full 200MHz BW of the ADC, to some 37MHz. This is 5 Nyquist zones, and which includes the 5th harmonic of a square wave at Nyquist. Although it is desirable to reduce noise BW, a filter with a steep transition band, or deep nulls in the stop band will ring in response to abrupt steps.

There are two aspects to settling of a filter that come into play when driving an ADC; the impulse response to the input waveform (related to S21 for RF engineers), and the reflection in response to the transients received from the ADC (S22). In a two port reflective filter, these are closely related. In an absorptive filter, or what could be regarded as a multiport filter, these can be disassociated from each other to an extent. Absorptive filters are crucial in achieving full performance from direct sampling ADCs. However, they tend to be more complex.

The time available for settling out in response to the disturbances from the LTC2387 is 1/fs-39nsec, or 27 nsec at 15Msps. A blighted reasoning would suggest that the 25 nsec settling of the LT1396 is adequate for this scenario. However, the amplifier must appear to settle from the perspective of the ADC, while interacting through the delayed response of the band-limiting filter, and this while driving the complex impedance of the filter. In addition, inter-dependent amplifiers result in extended settling time relative to that of a single amplifier. The differential input stage, composed of two CFAs, is however much less inter-dependent than if it were composed of voltage feedback amplifiers. To visualize this effect, for single ended input signals for example, the signal at the inverting input of the driven amplifier is directly buffered by the input stage, much like an emitter follower, and injected into the opposing amplifier, behaving as an inverting amplifier. This aspect dramatically improves the initial settling in response to fast input steps. On a happy note however, the filter mitigates the disturbance reflected into the amplifier. Fast settling of the output network is required for both high linearity from a direct sampling ADC, to dissipate any non-linear charge from the sampling process, and for imaging applications, perhaps to mitigate pattern noise. This typically means a Gaussian absorptive filter. Unfortunately, an absorptive filter is typically 2-3 times more complex than a reflective filter. Optimal damping in a driver such as this would require a filter with an impulse response that settles completely by the required settling time, in both directions, perhaps taking into consideration the slew rate of the amplifier. If the slew rates are asymmetrical, achieving optimal trade-off between settling and bandwidth for both excursions is unlikely, and the settling of the filter must be faster. Assuming symmetrical slewing, the optimal impulse response of the filter itself would be that with slewing of the amplifier involved rather than an ideal step. However, this would mean a different solution for different excursions if the amplifier is slew rate limited above some amplitude. Hence, the need for some slew rate limiting prior to the amplifier, as determined by C16 and C17. If the slew rate is limited prior to the amplifier, keeping the amplifier out of slew rate limiting, the filter should settle consistently for any amplitude excursion, and would be easier to correct in software. Keeping the amplifier out of slew limiting also prevents a large error voltage from developing across the inputs, keeping it out of non-linear operation, and avoiding an extended recovery process.

The common mode servo must operate into a pair of nodes that appear to be a real impedance, rather than reactive, and as a result, the output filter is again slightly more complicated than a simple reflective filter. These two nodes under control by a single amplifier must match, in terms of complex impedance, or it will translate the common mode errors, and noise of this amplifier into differential components, and would be seen by the ADC.

The control of reflections on transmission lines, and other elements involved in isolating the high speed path from a lower speed common mode loop also add complexity. This prototype board was designed to allow us to evaluate the LT1396 vs the AD8008, and other devices, in the MS8 package. There are other devices with different pin-outs that are faster settling, lower noise, and perhaps better suited to producing a compact layout. The use of resistors arrays had been considered, which may produce a more compact layout. If there is interest in this circuit, help is available, and the existing board can be made available in blank or partially populated form. The suitability of this driver must be evaluated for each sensor and application. However, the dynamic range, and fast settling of this topology may eliminate the need to customize for each type of sensor. That statement assumes that gain is low enough to accommodate the highest signal levels expected.

Other applications

For some applications, it may make sense to surrender half of the input range of the ADC and use, more importantly, uni-polar drive. Note that this means using 0V-4.096V differential drive to the ADC, not single ended drive. If a hypothetical imaging device were to have its lowest noise density in “darkness”, let’s call it darkness, darkness could be placed at bipolar zero. This means there is no need for injection of large scale offset, which is another potential source of 1/f noise. The 1/f region of the LTC2397 is very low at bipolar zero, not so low near full scale. Theoretically, accounting for folding of 5 Nyquist zones of noise BW from the amplifier, at reduced gain as may be expected using half the input range, the 1/f corner should be at approximately 1000 Hz with the AD8008, 600 Hz with LT1396, and possibly only some 10 Hz with the AD8002, at bipolar zero.

The 1/f corner of the ADC is not so low when the sensitivity to the voltage reference is maximized, near full scale. The 1/f corner is approx 15KHz with the internal reference, based on DC measurement near full scale. The 1/f corner of the AD8002 version is indeed visibly better at zero.

See part IV article on driving the LTC2387 reference for low 1/f over the entire range.

The use of the input stage with one input at 0V, and the other, receiving a ground referenced unipolar signal may require some changes to the common mode servo, and level shift control. I should have used two single amplifiers for the servos, as this would have made the board more flexible. The noise gain of the input stage could have been better preserved if the level shift control was able to use a more negative rail, with the output common mode servo perhaps on a single positive supply.

Used in this uni-polar fashion, this becomes rather like part III of this series, the trans-impedance application, but for faster rise times, or shorter pulses. This would only be suitable however, for applications where the pulses, or pixels, are synchronous with sampling, for example originating in pulsed excitation that is synchronous with sampling. If the gain were dropped by a factor of 2, in an AD8008 version, using only ½ the range of the ADC, the SNR would still be about 88dB, with the ADC now dominant, the amplifier’s contribution having dropped essentially 6dB.