Low Power IQ Modulator for Digital Communications

Low Power IQ Modulator for Digital Communications

Author's Contact Information

Bruce Hemp

Bruce Hemp


Sunny Hsiao

IQ modulators are versatile building blocks for RF systems. The most common application is generating RF signals for digital communication systems. This article illustrates the modulation accuracy of the LTC5599 low power IQ modulator, and shows by simple example how to integrate the device into a digital communication system.

What's an IQ Modulator?

An IQ modulator is a device that converts baseband information into RF signals. Internally, two double-balanced mixers are combined as shown below. By modulating with both in-phase (I) and quadrature (Q) inputs, any arbitrary output amplitude and phase can be selected.  

By targeting specific points in amplitude and phase, high order modulation is created. Shown below is 16-QAM. There are four possible I values, which decodes into two bits. Likewise for the Q axis. So each symbol can convey four bits of information.

Fundamental architecture of an IQ modulator

Modulator Applications

Virtually any type of RF modulation can be generated with IQ modulation, within the center frequency, bandwidth and accuracy capabilities of the modulator device. Table 1 shows some of the applications of the LTC5599.

Table 1. Some possible applications for the LTC5599 low power IQ modulator.
Application MOD STD Modulation Type(Reference 1) Max RF BW
Digital wireless microphones Proprietary QPSK, 16/32/64-DAPSK, Star-QAM 200kHz
Wireless networking
• White-space radios
• Cognitive radio
802.11af OFDM: BPSK, QPSK, 16/64/256-QAM Up to 4× 6MHz channels
CATV upstream DOCSIS 16-QAM 6MHz
Military radios (portable, manpack) Custom Wide programmability range
Software defined radios (SDR)
Portable test equipment
Analog modulation AM, FM/PM, SSB, DSB-SC
2-way radios
• Commercial
• Industrial
• Public safety
TETRA π/4-DQPSK, π/8-D8PSK, 4/16/64-QAM 25kHz to 150kHz
TETRAPOL GMSK 10kHz, 12.5kHz
P-25 C4FM, CQPSK 6.25kHz to 12.5kHz
DMR 4FSK 6.25kHz, 12.5kHz

Modulation Accuracy and EVM

The error vector magnitude or EVM is a measure of modulation accuracy in digital radio communication systems. Modulation accuracy is important because any error on the modulated signal can cause reception difficulty or excessive occupied bandwidth. If left unchecked, the receiver could exhibit excessive bit errors, the effective receiver sensitivity could be degraded or the transmit adjacent channel power (ACP) can become elevated.

An error vector is a vector in the I-Q plane between the actual received or transmitted symbol and the ideal reference symbol. EVM is the ratio of the average of the error vector power over the average ideal reference symbol vector power. It is frequently expressed in either dB or percentage.

Figure 1 is a test setup example showing the modulation accuracy attainable with the LT C5599 low power direct quadrature modulator. Figure 2 shows the results. In this test, precision lab equipment generates a 30k symbol/second 16-QAM baseband (120kbps), and 450MHz LO input signal to the modulator. A vector signal analyzer (VSA) examines the modulator output.

Figure 1. Test setup to measure basic modulation accuracy

Figure 2. LTC5599 EVM measured using lab-grade baseband and LO signal generators. Note that the MER measures over 49dB, basically “Broadcast Quality.”

In Figure 2, the EVM vs time results show EVM uniformly low across all symbols, while the error summary shows EVM approximately 0.24% RMS, and 0.6% peak. This is indeed excellent performance, shown by a modulation error ratio (MER) of 49.6dB.

The LTC5599 has internal trim registers that facilitate fine adjustments of I and Q DC offset, amplitude imbalance, and quadrature phase imbalance to further optimize modulation accuracy—results are even better if trim registers are adjusted.

In many ways, this test demonstrates the best-case capabilities of the modulator without optimization: baseband bandwidth is large, DAC accuracy and resolution are superb and digital filtering is nearly ideal.1 While these test results are useful for measuring the true performance of the modulator, practical low power wireless implementations necessitate some compromises, as discussed below.

Driving from Programmable Logic or an FPGA

Many FPGAs and programmable devices support digital filter block (DFB) functionality, an essential building block for digital communications. Raw transmit data is readily IQ mapped and digitally filtered. Figure 3 shows an example of how a device such as the Cypress PSoC 5LP can be utilized to drive IQ modulators such as the LTC5599.

Figure 3. Transmit exciter block diagram. (Full schematic is in Figure 4.)

Digital interpolation is used to increase the DAC clock frequency, and hence the DAC image frequencies. This lowers the filter order requirement of the LC reconstruct filter, which serves to attenuate DAC images to acceptable levels, while minimizing phase error and wideband noise.

Figure 4 shows the complete circuit. The differential baseband drive to the modulator, as opposed to single-ended baseband drive, offers the highest RF output power and lowest EVM. The LTC6238 low noise amplifier, U2, converts the DAC single-ended I and Q outputs to differential.2 Input amplifier U2 gain is designed to scale the DAC out voltage range to the modulator input voltage range, after the 2:1 attenuation effect of filter terminating resistors RL(I) and RL(Q) is taken into account. The input amplifier U2 is also designed to supply the required input common mode voltage for the IQ modulator—important for maintaining proper modulator DC operating point and linearity.

Figure 4. Driving an IQ modulator with programmable logic and DACs. The passive Bessel filter attenuates DAC images and provides lowest RF output noise floor, while imposing negligible symbol error vector.

Classical LC filter synthesis methods are used for the DAC reconstruction lowpass filter (LPF) design. Some of the filter shunt capacitance is implemented as common mode capacitors to ground. This also reduces common mode noise, which can find its way to the modulator output. If active filters are used here, the final filter stage before the modulator should be a passive LC roofing filter for lowest broadband RF noise floor.

Table 2. EVM performance. Even with a 63-tap FIR filter design and 8-bit dual-DACs, the 0.8% RMS EVM achievement is entirely adequate for most applications.
TX FIR Filter Design Interpolation Factor Symbol Rate (ksps) Data Rate (kbps) EVM (% RMS) EVM (% PEAK) Notes
63-tap RRC, α = 0.35 8 30 120
0.8 2.0 LTC5599 Unadjusted (MER = 39.1dB)
0.8 1.8 LTC5599 Adjusted (MER = 39.8dB)

Table 2, Figure 5 and Figure 6 show the performance results. In this case, EVM is limited by the digital accuracy of the baseband waveforms, here determined by the number of U1 FIR filter taps (63), and by the DAC resolution (eight bits). For this reason, EVM does not substantially improve when IQ modulator impairments are adjusted out, as shown in Table 2. For lower EVM, use more FIR filter taps and higher resolution DACs.

Figure 5. EVM measurement detail. Two IC devices replace the lab signal generator. It’s not perfect, but is usually ‘good enough.’

Figure 6. Output spectrum. In this design, the closest image spurs are about 70dB down, reasonably good for most systems. Modulator RMS output power measures −4dBm. Harmonic filtering is still required.

When comparing the results shown in Figures 2 and 5, we see the price paid for replacing a high grade lab signal generator with a circuit composed of programmable logic and op amp filters. EVM increased from 0.24% RMS to 0.8% RMS. The increased EVM is primarily due to the fact that the waveforms generated by the programmable logic IC are not as accurate as the lab instrument. Such is the case in a real world implementation, but Figure 5 shows a fairly decent eye diagram, and a summary measurement that shows the modulation accuracy is sufficient for most applications.

In Figure 6 we see the output spectrum is quite clean. The amplitude of the DAC image spurs, relative to the desired signal, is estimated by sin(x)/x, where x = πf/fCLK, plus attenuation afforded by the DAC LC reconstruct filter. For lowest adjacent channel power, a long FIR filter (many taps) is essential, as is a low phase noise LO.

Higher frequency span sweeps show no visible spurious products except for the harmonics of the carrier, which must be filtered as usual.

Low output noise floor is also important in many cases, such as when a transmitter and receiver are duplexed or co-located, when high PA gain is used, or when multiple transmitters run simultaneously. Table 3 shows the measured output noise density for the system of Figure 3, while transmitting at a modulated carrier frequency of 460MHz. The low U2 op amp noise, combined with the 5th order roll-off of the LC reconstruct filter, keeps the baseband noise contribution as low as possible.

Table 3. Output noise density levels off at approximately 17dB over kTB.
Frequency Offset (MHz) RF Output Noise Density (dBM/Hz)
+6 −156.7
+10 −156.8
+20 −156.8

Total current consumption at 3.3V measures 96mA, as summarized in Table 4. The majority of the DC power is consumed by U1, the programmable logic device, for which each DFB is specified to typically consume 21.8mA at the 67MHz clock frequency of this application.3 In summary, the DFBs account for 81% of the digital power consumption. Clearly the key to reduced current consumption for the digital section is optimization of the DFB architecture, which is beyond the scope of this article.4

Table 4. Total power consumption
Stage Description ICC (mA) Power (mW)
U1 CY8C58LP Programmable System on Chip 54 178
U2 LT6238 Quad Op Amp 13 43
U3 LTC5599 Low Power IQ Modulator 29 96
Total: 96 317


Linear Technology’s LTC5599 IQ modulator is a versatile RF building block, offering low power consumption, high performance, wide frequency range and unique optimization capabilities. It simplifies radio transmitter design without sacrificing performance or efficiency.


1 Test equipment FIR filters are synthesized in software, so hundreds or thousands of filter taps are feasible and preferred, since signal quality is most important, and delay is inconsequential. In contrast, a real-time wireless application typically requires trade-offs between filter delay and EVM/ACP.

2 For lower symbol rate applications, the LTC1992 low power fully differential input/output amplifier/driver could also be used for this purpose, offering improved DC accuracy and lower DC power consumption in exchange for a higher transmit noise floor within the channel passband.

3 In this example, the minimum DFB clock frequency = 30kHz symbol rate • 8x interpolation • 63 FIR filter taps • 2 cycles for multiply and accumulate (MAC) • 2 cycles for arithmetic logic (ALU) = 60.5MHz.

4 DFBs that are faster and more highly optimized are available from Altera and Xilinx.