When evaluating the performance of a SAR ADC it is frequently necessary to level shift the output of your signal source to conform to the ADC input range requirements. Typically your choices are to use the DC offset of the signal source if that is an option on your generator or AC couple the signal source output. Generator DC offsets when available usually introduce noticeable distortion. AC coupling the signal works well at frequencies above 20 kHz but as the frequency of interest goes lower, larger value capacitors are required to pass the signal without attenuation or distortion. At an input frequency of 1 to 2 kHz where many 16-bit to 20-bit SAR ADCs are specified, finding a suitable coupling capacitor is often not practical.
The circuit of Figure 1 provides an alternative to using the generator’s DC offset or AC coupling the signal. R2, R1 and the source impedance of the generator (The source impedance of the Stanford Research SR1 generator used is 25Ω. R1 will need to be adjusted if the generator you are using has different source impedance.) form a voltage divider which as shown in the circuit of Figure 1 converts a ±5V signal to 0 - 5V. R1 and R2 need to be low impedance to minimize errors caused by the input current of whatever is being driven by this circuit. By adjusting the +5V node other voltage ranges are possible. C2 forms a 2.1 kHz lowpass filter with R2, R1 and the generator source impedance. To keep distortion low, it is important that the +5V node does not move as the input voltage changes. Because many lab supplies cannot source and sink current, resistor R3 is used to preload the +5V node to help keep it constant. C1 is a bypass capacitor for the +5V node.
Figure 1. Low Distortion Level Shift Circuit Converts ±5V Signal to 0-5V.
Figure 2 shows the input and output voltages of the circuit of Figure 1 with a 100Hz input signal. Trace 1 is the input and Trace 2 is the output. Figure 3 shows the FFT of the circuit’s output with a 2 kHz input signal. The THD is –119dB and the SNR is 112dB which is adequate for even 20-bit ADCs.
Figure 2. Input (Trace 1) and Output (Trace 2) voltages of the circuit of Figure 1.
Figure 3. FFT of the Output of the Circuit of Figure 1.
